xenia-rs/migration/project-root/ppc-manual/fpu/fcfidx.md

fcfidx — Floating Convert From Integer Doubleword

Category: Floating-Point · Form: X · Opcode: 0xfc00069c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fcfid	fcfidx	—	Floating Convert From Integer Doubleword
fcfid.	fcfidx	Rc=1	Floating Convert From Integer Doubleword

Syntax

fcfid[Rc] [FD], [FB]

Encoding

fcfidx — form X

• Opcode word: 0xfc00069c
• Primary opcode (bits 0–5): 63
• Extended opcode: 846
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fcfidx: read	Source B floating-point register.
FD	fcfidx: write	Destination floating-point register.
CR	fcfidx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fcfidx: write	Floating-Point Status and Control Register.

Register Effects

fcfidx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fcfidx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fcfidx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fcfidx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:253
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:27
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:914
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2872-2885

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fcfidx => {
            // Convert from integer doubleword: frD = (double)(int64_t)frB_as_bits.
            // PPCBUG-224: set XX when |i64| > 2^53 (precision loss in conversion).
            let bits = ctx.fpr[instr.rb()].to_bits();
            let i = bits as i64;
            let result = i as f64;
            if (result as i64) != i {
                fpscr::set_exception(ctx, fpscr::XX);
            }
            ctx.fpr[instr.rd()] = result;
            fpscr::set_fprf(ctx, fpscr::classify_fprf(result));
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 64-bit signed integer → binary64. Reads FRB as a 64-bit signed integer (the bits, interpreted as i64) and converts it to IEEE-754 binary64. xenia-rs implements this as bits as i64 as f64.
• Loss of precision. binary64 has 53 bits of significand, so i64 values with magnitude > 2^53 lose low-order bits. This raises FPSCR[XX, FX] (inexact) on hardware. xenia-rs does not update FPSCR (xenia quirk) but the rounded value matches host f64 rules (round-to-nearest-even by default).
• Always exact for |x| <= 2^53. Within ±9,007,199,254,740,992 the conversion is bit-exact.
• Rounding mode. Uses FPSCR[RN]. Default nearest-even. Rust's as f64 from i64 uses platform-native conversion which on Xenon-target hosts will respect the FE rounding mode; xenia uses the host default.
• No NaN/∞ generation. All i64 inputs map to finite f64 outputs (the largest i64 is well below f64::MAX).
• FPSCR side effects. Hardware updates FPRF (result class) and may set XX/FX on inexact. xenia does not update FPSCR.
• Rc=1 (fcfid.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 846. Reads FRB only.
• Common pairing. Used after lfd of a stored i64 to bring an integer into the FP pipeline for arithmetic; the inverse direction is fctidx / fctidzx.

Related Instructions

• fctidx, fctidzx — inverse direction (binary64 → 64-bit integer, current rounding / round-toward-zero).
• fctiwx, fctiwzx — 32-bit integer conversion variants.
• frspx — round to single precision; commonly chained after fcfid to produce a float.
• lfd, stfd — load/store doubleword used to move integer values between GPR and FPR via memory.
• mffsx, mtfsfx — control rounding mode used by the conversion.

IBM Reference

• AIX 7.3 — fcfid (Floating Convert From Integer Doubleword)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (integer→FP conversion semantics).