xenia-rs/migration/project-root/ppc-manual/fpu/frspx.md

frspx — Floating Round to Single

Category: Floating-Point · Form: X · Opcode: 0xfc000018

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
frsp	frspx	—	Floating Round to Single
frsp.	frspx	Rc=1	Floating Round to Single

Syntax

frsp[Rc] [FD], [FB]

Encoding

frspx — form X

• Opcode word: 0xfc000018
• Primary opcode (bits 0–5): 63
• Extended opcode: 12
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	frspx: read	Source B floating-point register.
FD	frspx: write	Destination floating-point register.
CR	frspx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	frspx: write	Floating-Point Status and Control Register.

Register Effects

frspx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• frspx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

frspx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="frspx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:318
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:29
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:898
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2856-2871

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::frspx => {
            // Round to single precision honouring FPSCR[RN].
            // PPCBUG-225: set XX on inexact rounding (almost every frsp call).
            let b = ctx.fpr[instr.rb()];
            if fpscr::is_snan(b) {
                fpscr::set_exception(ctx, fpscr::VXSNAN);
            }
            let result = to_single(ctx, b);
            if b.is_finite() && result.is_finite() && result != b {
                fpscr::set_exception(ctx, fpscr::XX);
            }
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, b.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Round to single-precision. Rounds the binary64 value in FRB to binary32 using FPSCR[RN], then re-encodes the result back into the destination as a binary64 representation of that single value. xenia-rs uses to_single(b), which performs f64 → f32 → f64 round-trip (Rust's as f32 uses round-to-nearest-even, matching the PPC default).
• FPSCR[RN] not honored in xenia. Like other conversion ops, xenia's to_single is hard-coded to round-to-nearest-even regardless of FPSCR[RN]. xenia quirk for non-default rounding modes.
• Overflow. Values whose magnitude exceeds binary32's max (~3.4e38) round to ±∞ and set FPSCR[OX, XX, FX].
• Underflow. Values whose magnitude is below binary32's smallest normal (~1.2e-38) flush to zero or denormal per FPSCR[NI]; UX/XX/FX set on hardware. xenia uses host IEEE.
• NaN propagation. Quiet NaNs pass through; signalling NaNs are quietened (sign-bit cleared on the SNaN-quietening payload bit). Host as f32 does not perform PPC-style quietening; xenia quirk for SNaN bit-level inspection.
• Inexact. Most rounding produces inexact; sets FPSCR[XX, FX]. xenia does not update FPSCR (xenia quirk).
• Rc=1 (frsp.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 12. Reads FRB only.
• Use case. Compilers emit frsp after a chain of fadd/fmul/etc. when storing the value with stfs (store single). Without an explicit frsp, the in-FPR double would not match the stfs-rounded single.

Related Instructions

• faddsx, fsubsx, fmulsx, fdivsx — single-precision arithmetic; equivalent to frsp(double_op(...)).
• fmaddsx, fmsubsx, fnmaddsx, fnmsubsx — single-precision fused FMA family.
• stfs — store single; expects an FPR already rounded to single via frsp or via single-precision arithmetic.
• fcfidx — fcfid + frsp is the standard i64 → float conversion.
• mffsx, mtfsfx — FPSCR rounding-mode control.

IBM Reference

• AIX 7.3 — frsp (Floating Round to Single)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (single-precision rounding rules; SNaN quietening).