e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
131 lines
5.8 KiB
Markdown
131 lines
5.8 KiB
Markdown
# `fsubx` — Floating Subtract
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> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xfc000028`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `fsub` | `fsubx` | — | Floating Subtract |
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| `fsub.` | `fsubx` | Rc=1 | Floating Subtract |
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## Syntax
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```asm
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fsub[Rc] [FD], [FA], [FB]
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```
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## Encoding
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### `fsubx` — form `A`
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- **Opcode word:** `0xfc000028`
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- **Primary opcode (bits 0–5):** `63`
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- **Extended opcode:** `20`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (59 or 63) |
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| 6–10 | `FRT` | destination FPR |
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| 11–15 | `FRA` | source A FPR |
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| 16–20 | `FRB` | source B FPR |
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| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
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| 26–30 | `XO` | extended opcode (5 bits) |
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| 31 | `Rc` | record-form flag (updates CR1) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `FA` | fsubx: read | Source A floating-point register (`fr0`–`fr31`). |
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| `FB` | fsubx: read | Source B floating-point register. |
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| `FD` | fsubx: write | Destination floating-point register. |
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| `CR` | fsubx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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| `FPSCR` | fsubx: write | Floating-Point Status and Control Register. |
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## Register Effects
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### `fsubx`
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- **Reads (always):** `FA`, `FB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`, `FPSCR`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `fsubx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
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## Operation (pseudocode)
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```
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FRT <- FRA − FRB
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`fsubx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fsubx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:127`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L127)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:30`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L30)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:921`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L921)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2575-2584`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2575-L2584)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::fsubx => {
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let a = ctx.fpr[instr.ra()];
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let b = ctx.fpr[instr.rb()];
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fpscr::check_invalid_add(ctx, a, b, true);
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let result = a - b;
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ctx.fpr[instr.rd()] = result;
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fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite());
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if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Double precision.** `fsub` operates on IEEE-754 binary64. The single-precision sibling is [`fsubsx`](fsubsx.md), which rounds the result to binary32 before re-encoding it into the 64-bit FPR.
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- **`±∞ − ±∞` is the canonical invalid case.** Same-signed infinity subtraction (or opposite-signed addition) yields `QNaN(VXISI)` and sets `FPSCR[VXISI, VX, FX]`.
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- **FPSCR side effects.** Hardware updates `FPRF`, `FR`, `FI`, `FX` plus exception bits `OX`, `UX`, `XX`, `VXISI`, `VXSNAN` as appropriate. xenia-rs's interpreter does **not** model FPSCR updates — a xenia quirk that almost never matters in practice.
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- **`Rc=1` (`fsub.`)** writes `CR1` from `FPSCR[FX, FEX, VX, OX]`.
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- **NaN propagation.** Any NaN operand yields a quiet NaN; a signalling NaN input is quietened (signalling bit cleared) per PowerISA. Host `f64 -` is relied on for the value.
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- **Sign of zero.** `+0 − +0 = +0` in round-to-nearest, `−0` in round-toward-negative-infinity. xenia inherits host semantics.
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- **Denormal flush.** Xenon boots with `FPSCR[NI]=1` (non-IEEE mode) so subnormal results flush to zero on hardware. Xenia produces IEEE-compliant denormals from the host FPU; titles relying on flush-to-zero typically see no observable difference for game logic but may see subtle differences in audio DSP.
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- **Encoding.** A-form, primary 63, XO 20. `FRC` is don't-care for sub.
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## Related Instructions
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- [`fsubsx`](fsubsx.md) — single-precision subtract (rounds to binary32).
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- [`faddx`](faddx.md), [`faddsx`](faddsx.md) — add counterparts; subtract is implemented as add-with-negated-B on most cores.
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- [`fnegx`](fnegx.md) — sign flip (the bit-pattern operation behind `−FRB`).
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- [`fmsubx`](fmsubx.md), [`fnmsubx`](fnmsubx.md) — fused multiply-subtract (single rounding step).
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- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md), [`mtfsb0x`](mtfsb0x.md), [`mtfsb1x`](mtfsb1x.md) — FPSCR control.
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## IBM Reference
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- [AIX 7.3 — `fsub` (Floating Subtract)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fs-fsub-floating-subtract-instruction)
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- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/).
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