e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
117 lines
4.7 KiB
Markdown
117 lines
4.7 KiB
Markdown
# `dcbtst` — Data Cache Block Touch for Store
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0001ec`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `dcbtst` | `dcbtst` | — | Data Cache Block Touch for Store |
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## Syntax
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```asm
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dcbtst [RA0], [RB]
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```
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## Encoding
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### `dcbtst` — form `X`
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- **Opcode word:** `0x7c0001ec`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `246`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | dcbtst: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | dcbtst: read | Source GPR. |
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## Register Effects
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### `dcbtst`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`dcbtst`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="dcbtst"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1150`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1150)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:19`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L19)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:792`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L792)
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Hint, not a guarantee.** `dcbtst` requests the addressed cache line be brought into L1 in anticipation of a future **store**. Hardware may treat this as a hint to fetch in an exclusive coherence state to avoid a follow-up upgrade.
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- **Pair of [`dcbt`](dcbt.md).** `dcbt` signals read intent; `dcbtst` signals write intent. Use `dcbtst` before a planned store loop to avoid stalling on cache-line acquisition.
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- **No exception on bad address.** Like `dcbt`, prefetch hints to unmapped or protected pages are silently dropped — no DSI exception. Safe to issue speculatively.
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- **Cache line size.** Xenon line is 128 bytes; the low seven bits of `EA` are ignored.
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- **`RA0` semantics.** `RA = 0` selects literal zero — `dcbtst 0, RB` prefetches the line containing address `RB`.
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- **Often replaced by `dcbz128`.** When code knows it will write the **entire** line, `dcbz128` is preferable: it allocates the line and zeros it without reading from memory at all, beating `dcbtst` + first-store.
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- **Xenia treats as no-op.** Hints have no observable effect under the emulated memory model.
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## Related Instructions
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- [`dcbt`](dcbt.md) — read-intent prefetch.
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- [`dcbz`](dcbz.md), `dcbz128` — allocate-and-zero (skip the read entirely when writing the whole line).
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- [`dcbf`](dcbf.md), [`dcbst`](dcbst.md), [`dcbi`](dcbi.md) — push / invalidate counterparts.
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- [`icbi`](icbi.md) — instruction-cache invalidate.
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## IBM Reference
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- [AIX 7.3 — `dcbtst` (Data Cache Block Touch for Store)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-dcbtst-data-cache-block-touch-store-instruction)
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- `PowerISA v2.07B Book II` § "Storage Control Instructions".
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