xenia-rs/migration/project-root/ppc-manual/memory/ldarx.md

ldarx — Load Doubleword and Reserve Indexed

Category: Memory · Form: X · Opcode: 0x7c0000a8

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
ldarx	ldarx	—	Load Doubleword and Reserve Indexed

Syntax

ldarx [RD], [RA0], [RB]

Encoding

ldarx — form X

• Opcode word: 0x7c0000a8
• Primary opcode (bits 0–5): 31
• Extended opcode: 84
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	ldarx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	ldarx: read	Source GPR.
RD	ldarx: write	Destination GPR.

Register Effects

ldarx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

ldarx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="ldarx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:765
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:36
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:772
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4559-4573

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::ldarx => {
            let ea = ea_indexed(ctx, instr);
            let val = mem.read_u64(ea);
            ctx.gpr[instr.rd()] = val;
            ctx.reserved_line = ea & !RESERVATION_MASK;
            ctx.reserved_val = val;
            ctx.has_reservation = true;
            ctx.reservation_width = 8; // PPCBUG-151: doubleword reservation
            if let Some(t) = &ctx.reservation_table {
                if t.is_enabled() {
                    ctx.reserved_generation = t.reserve(ea, ctx.hw_id);
                }
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Reservation set. Loads the doubleword at EA and atomically establishes a reservation on that address. A subsequent stdcx at the same address completes only if the reservation is still valid. Together they form a standard load-linked / store-conditional pair for lock-free updates.
• One reservation per thread. Xenia tracks reserved_addr / reserved_val / has_reservation per-context (see snapshot). Hardware behaves the same: each hardware thread holds at most one reservation at a time. A new ldarx (or lwarx) discards the prior reservation.
• Granule. Architecturally the reservation covers a single naturally-aligned doubleword (8 bytes). On Xenon the practical reservation granule is one cache line (128 bytes) — any store to that line by another agent loses the reservation. Xenia simplifies to per-address tracking.
• Alignment requirement. EA must be 8-byte aligned. An unaligned ldarx raises an alignment exception on hardware. Xenia does not check; pass aligned addresses.
• RA0 semantics. When RA = 0, base is literal zero — ldarx RT, 0, RB reads at exact RB. Used in synthetic-zero atomic-init idioms, but rare.
• Reservation-loss events. Any exception, context switch, or store by another thread to the reserved line clears the reservation. Application code must treat the stdcx failure as a normal retry condition, not as an error.
• Pair atomically. Code must be ldarx ... do work ... stdcx. with no intervening loads or stores that could be re-ordered. Optionally fence with lwsync inside the loop. The conditional store sets CR0[EQ] to report success.

Related Instructions

• stdcx — store-conditional doubleword (the matching half of the pair).
• lwarx / stwcx — 32-bit reservation pair.
• ld, ldx — non-reserving doubleword loads.
• sync, lwsync — barriers commonly placed around reservation pairs.

IBM Reference

• AIX 7.3 — ldarx (Load Doubleword and Reserve Indexed)
• PowerISA v2.07B Book II § "Atomic Update Primitives" for full reservation semantics and granule rules.