xenia-rs/migration/project-root/ppc-manual/memory/ldbrx.md

ldbrx — Load Doubleword Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c000428

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
ldbrx	ldbrx	—	Load Doubleword Byte-Reverse Indexed

Syntax

ldbrx [RD], [RA0], [RB]

Encoding

ldbrx — form X

• Opcode word: 0x7c000428
• Primary opcode (bits 0–5): 31
• Extended opcode: 532
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	ldbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	ldbrx: read	Source GPR.
RD	ldbrx: write	Destination GPR.

Register Effects

ldbrx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

ldbrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="ldbrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:654
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:36
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:816
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4627-4631

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::ldbrx => {
            let ea = ea_indexed(ctx, instr);
            ctx.gpr[instr.rd()] = mem.read_u64(ea).swap_bytes();
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Reads little-endian. ldbrx loads 8 bytes and reverses byte order before placing them in RT. With Xenon's PowerPC big-endian world view, the architectural effect is "load a little-endian doubleword as if it were big-endian" — useful when consuming network buffers, file headers (PNG IHDR, ZIP CRC32, etc.), or PC-side data structures that store little-endian.
• Implementation detail. The xenia snapshot calls mem.read_u64(ea).swap_bytes(). read_u64 already returns the host-native value of the big-endian doubleword at EA; swap_bytes then flips it, giving the little-endian interpretation. Equivalent to four sequential lbz plus shifts, but issued as one micro-op.
• No update form, X-form only. PowerPC byte-reverse loads come in indexed form only (no ldbrxu or DS-form). EA = (RA|0) + RB. To increment a pointer, fold the increment into RB or use a separate addi.
• RA0 semantics. When RA = 0, base is the literal zero; ldbrx RT, 0, RB reads at exact RB.
• Alignment. Like the rest of the byte-reverse family, ldbrx does not require natural alignment on hardware; the load is done as eight byte reads internally. Xenon may take an alignment exception on cache-inhibited storage.
• No corresponding sign-extension. The output is the literal byte-reversed bit pattern; it occupies the full 64-bit register. Use shifts or extsw/extsh afterwards if a sign-extended narrower datum is desired.
• Pair with stdbrx. The store side performs the inverse: takes the GPR value, reverses, writes 8 bytes.

Related Instructions

• stdbrx — store doubleword byte-reverse indexed.
• lwbrx, lhbrx — narrower byte-reverse loads (word, halfword).
• stwbrx, sthbrx — narrower byte-reverse stores.
• ld, ldx — non-reversing doubleword loads.

IBM Reference

• AIX 7.3 — ldbrx (Load Doubleword Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".