xenia-rs/migration/project-root/ppc-manual/memory/lhbrx.md

lhbrx — Load Half Word Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c00062c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lhbrx	lhbrx	—	Load Half Word Byte-Reverse Indexed

Syntax

lhbrx [RD], [RA0], [RB]

Encoding

lhbrx — form X

• Opcode word: 0x7c00062c
• Primary opcode (bits 0–5): 31
• Extended opcode: 790
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lhbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lhbrx: read	Source GPR.
RD	lhbrx: write	Destination GPR.

Register Effects

lhbrx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lhbrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lhbrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:628
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:40
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:839
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1806-1812

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lhbrx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            let val = mem.read_u16(ea);
            ctx.gpr[instr.rd()] = val.swap_bytes() as u64;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Reads little-endian half. Loads 2 bytes and swaps them: byte at EA becomes the low 8 bits of RT[16:23], byte at EA+1 becomes the upper 8 bits. The xenia snapshot does mem.read_u16(ea).swap_bytes(). Effective for parsing little-endian on-disk or network half-word fields.
• Zero-extension to 64 bits. Result occupies the full 64-bit GPR; high 48 bits are zero. There is no sign-extending byte-reverse load (lhbrx + extsh if you need one).
• X-form only — no update form. Like all byte-reverse loads, only the indexed form exists. EA = (RA|0) + RB. Pointer-bumping requires a separate addi.
• RA0 semantics. When RA = 0, base is the literal zero — lhbrx RT, 0, RB reads at exact RB.
• Alignment. Hardware tolerates unaligned half-word reads. Xenon may take alignment exceptions on cache-inhibited storage.
• Common in stream parsers. PNG, ZIP, BMP, WAV chunk decoders use lhbrx to read little-endian length fields.

Related Instructions

• lwbrx, ldbrx — wider byte-reverse loads.
• sthbrx — store-half byte-reverse counterpart.
• lhz, lhzx — non-reversing zero-extending half loads.
• lha — non-reversing sign-extending half load.

IBM Reference

• AIX 7.3 — lhbrx (Load Half Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".