e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
131 lines
5.3 KiB
Markdown
131 lines
5.3 KiB
Markdown
# `lwbrx` — Load Word Byte-Reverse Indexed
|
||
|
||
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00042c`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `lwbrx` | `lwbrx` | — | Load Word Byte-Reverse Indexed |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
lwbrx [RD], [RA0], [RB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `lwbrx` — form `X`
|
||
|
||
- **Opcode word:** `0x7c00042c`
|
||
- **Primary opcode (bits 0–5):** `31`
|
||
- **Extended opcode:** `534`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT/FRT/VRT` | destination |
|
||
| 11–15 | `RA/FRA/VRA` | source A |
|
||
| 16–20 | `RB/FRB/VRB` | source B |
|
||
| 21–30 | `XO` | extended opcode (10 bits) |
|
||
| 31 | `Rc` | record-form flag |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `RA0` | lwbrx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
|
||
| `RB` | lwbrx: read | Source GPR. |
|
||
| `RD` | lwbrx: write | Destination GPR. |
|
||
|
||
## Register Effects
|
||
|
||
### `lwbrx`
|
||
|
||
- **Reads (always):** `RA0`, `RB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `RD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
; Pseudocode derives directly from the xenia-rs interpreter
|
||
; arm (see Implementation References). Operation semantics:
|
||
; - Read source operands from the fields listed under Operands.
|
||
; - Apply the arithmetic / logical / memory action described
|
||
; in the Description field above.
|
||
; - Write results to the destination register(s); update any
|
||
; status bits enumerated under Status-Register Effects.
|
||
; Consult the IBM AIX reference link under IBM Reference for
|
||
; canonical PPC-style pseudocode where xenia's expression is
|
||
; terse.
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* C translation: the xenia-rs interpreter arm below in */
|
||
/* Implementation References is the authoritative semantic */
|
||
/* snapshot. Translate it line-by-line: */
|
||
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
|
||
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
|
||
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
|
||
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`lwbrx`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lwbrx"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:641`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L641)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:49`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L49)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:818`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L818)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1799-1805`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1799-L1805)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::lwbrx => {
|
||
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
|
||
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
|
||
let val = mem.read_u32(ea);
|
||
ctx.gpr[instr.rd()] = val.swap_bytes() as u64;
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **Reads little-endian word.** Loads 4 bytes and reverses byte order. With Xenon's big-endian world view, the architectural effect is "load a little-endian word as if it were big-endian" — the standard parser instruction for PNG/ZIP/RIFF/TGA chunk fields, network protocol fields, and PC-side-formatted data.
|
||
- **Implementation detail.** The xenia snapshot calls `mem.read_u32(ea).swap_bytes()`. `read_u32` already returns the host-native value of the big-endian word at `EA`; `swap_bytes` then flips it.
|
||
- **X-form only — no update form.** Only the indexed form exists. `EA = (RA|0) + RB`. Pointer-bumping requires a separate `addi`.
|
||
- **`RA0` semantics.** When `RA = 0`, base is literal zero; `lwbrx RT, 0, RB` reads at exact `RB`.
|
||
- **Zero-extension to 64 bits.** Result occupies the full 64-bit GPR; high 32 bits zero. There is no sign-extending byte-reverse load — combine with `extsw` if needed.
|
||
- **Alignment.** Hardware tolerates unaligned 4-byte reads. Cache-inhibited storage may raise alignment exceptions on real Xenon.
|
||
- **Pair with [`stwbrx`](stwbrx.md).** Symmetric byte-reverse store.
|
||
|
||
## Related Instructions
|
||
|
||
- [`lhbrx`](lhbrx.md), [`ldbrx`](ldbrx.md) — narrower / wider byte-reverse loads.
|
||
- [`stwbrx`](stwbrx.md) — store-word byte-reverse counterpart.
|
||
- [`lwz`](lwz.md), [`lwzx`](lwz.md) — non-reversing zero-extending word loads.
|
||
- [`lwa`](lwa.md), [`lwax`](lwa.md) — non-reversing sign-extending word loads.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `lwbrx` (Load Word Byte-Reverse Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lwbrx-load-word-byte-reverse-indexed-instruction)
|
||
- `PowerISA v2.07B Book II` § "Byte-Reverse Storage Access".
|