xenia-rs/migration/project-root/ppc-manual/memory/stdbrx.md

stdbrx — Store Doubleword Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c000528

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stdbrx	stdbrx	—	Store Doubleword Byte-Reverse Indexed

Syntax

stdbrx [RS], [RA0], [RB]

Encoding

stdbrx — form X

• Opcode word: 0x7c000528
• Primary opcode (bits 0–5): 31
• Extended opcode: 660
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	stdbrx: read	Source GPR (alias for RD in some stores).
RA0	stdbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stdbrx: read	Source GPR.

Register Effects

stdbrx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stdbrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stdbrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:691
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:69
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:829
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4632-4639

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stdbrx => {
            let ea = ea_indexed(ctx, instr);
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_u64(ea, ctx.gpr[instr.rs()].swap_bytes());
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Writes little-endian doubleword. Reverses the 8 bytes of RS and stores them at EA. Compared to a regular std, the byte at EA becomes RS[56:63] (least-significant), and the byte at EA+7 becomes RS[0:7] (most-significant). The xenia snapshot calls mem.write_u64(ea, ctx.gpr[instr.rs()].swap_bytes()).
• Used to emit little-endian payloads. Symmetric counterpart of ldbrx. Common when writing PC-side file formats, network packets, or PE/COFF headers from PowerPC code.
• X-form only — no update form, no DS-form. Only the indexed form exists. EA = (RA|0) + RB. Pointer-bumping requires a separate addi.
• RA0 semantics. When RA = 0, base is literal zero. stdbrx RS, 0, RB writes at exact RB.
• Alignment. Hardware tolerates unaligned 8-byte writes. Cache-inhibited storage may raise alignment exceptions on real hardware.
• No CR / FPSCR effects. Pure data movement.
• Cache-line straddling cost. As with std, writes that cross a 128-byte line boundary touch two cache lines; keep doublewords 8-byte aligned for best performance.

Related Instructions

• ldbrx — load doubleword byte-reverse (the matching load).
• stwbrx, sthbrx — narrower byte-reverse stores.
• std, stdx — non-reversing doubleword stores.

IBM Reference

• AIX 7.3 — stdbrx (Store Doubleword Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".