xenia-rs/migration/project-root/ppc-manual/memory/stmw.md

stmw — Store Multiple Word

Category: Memory · Form: D · Opcode: 0xbc000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stmw	stmw	—	Store Multiple Word

Syntax

(no disassembly template)

Encoding

stmw — form D

• Opcode word: 0xbc000000
• Primary opcode (bits 0–5): 47
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description

Register Effects

stmw

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stmw

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stmw"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:527
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:75
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:370
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1735-1759

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stmw => {
            let mut ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            ea = ea.wrapping_add(instr.d() as i64 as u64);
            // PPCBUG-160: stmw can span two cache lines when (32-rs)*4 > one line.
            // Iterate over every touched line so any reservation on a later line
            // is also invalidated (same guarantee as single-word stores).
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() {
                    let start_ea = ea as u32;
                    let last_ea = start_ea.wrapping_add((32 - instr.rs() as u32) * 4).wrapping_sub(1);
                    let line_size = RESERVATION_MASK + 1;
                    let mut line = start_ea & !RESERVATION_MASK;
                    loop {
                        t.invalidate_for_write(line);
                        if line >= (last_ea & !RESERVATION_MASK) { break; }
                        line = line.wrapping_add(line_size);
                    }
                }
            }
            for r in instr.rs()..32 {
                mem.write_u32(ea as u32, ctx.gpr[r] as u32);
                ea = ea.wrapping_add(4);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Bulk register save. Stores (32 - RS) consecutive 32-bit words taken from r[RS], r[RS+1], …, r31 to memory starting at EA. The symmetric counterpart of lmw. Used by AIX/PowerPC ABI prologues to save non-volatile GPRs in one instruction.
• Each store is the low 32 bits of the GPR. Xenia's snapshot writes ctx.gpr[r] as u32 — only the low half of the 64-bit GPR. The high 32 bits are discarded; stmw cannot save 64-bit values (use a sequence of std instead).
• Big-endian write. Word from r[RS] lands at EA, word from r[RS+1] at EA+4, etc. Each word is itself written most-significant-byte first.
• RA0 semantics. When RA = 0, base is the literal zero. Useful for absolute-address restoration.
• Alignment. PowerISA requires word-aligned EA; an unaligned stmw may raise an alignment exception on hardware. Xenia tolerates it.
• Performance trap. Modern PowerPC implementations microcode stmw — typically slower than the same number of stw instructions. Compilers prefer the unrolled form.
• Cache-line behaviour. When the run of words crosses several 128-byte cache lines, each cold line triggers a read-allocate. Pre-clearing with dcbz128 helps for fresh frames.

Related Instructions

• lmw — symmetric "load multiple words" (the matching epilogue partner).
• stw, stwx — single-word stores; the modern preferred form.
• stswi, stswx — store string (byte-granular bulk transfer).
• std — for 64-bit values (no "store multiple doubleword" exists).

IBM Reference

• AIX 7.3 — stmw (Store Multiple Word)
• PowerISA v2.07B Book II § "Load and Store Multiple".