xenia-rs/migration/project-root/ppc-manual/memory/stswx.md

stswx — Store String Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00052a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stswx	stswx	—	Store String Word Indexed

Syntax

(no disassembly template)

Encoding

stswx — form X

• Opcode word: 0x7c00052a
• Primary opcode (bits 0–5): 31
• Extended opcode: 661
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

stswx

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stswx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stswx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:742
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:75
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:830
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4663-4689

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stswx => {
            let mut ea = ea_indexed(ctx, instr);
            let nb = ctx.xer() & 0x7F;
            let mut rs = instr.rs();
            let mut bytes_left = nb;
            if nb > 0 {
                if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                    if t.has_active_reservers() {
                        let first_line = ea & !RESERVATION_MASK;
                        let last_line = ea.wrapping_add(nb - 1) & !RESERVATION_MASK;
                        t.invalidate_for_write(first_line);
                        if last_line != first_line { t.invalidate_for_write(last_line); }
                    }
                }
            }
            while bytes_left > 0 {
                let val = ctx.gpr[rs] as u32;
                for byte_idx in 0..4 {
                    if bytes_left == 0 { break; }
                    mem.write_u8(ea, (val >> (24 - byte_idx * 8)) as u8);
                    ea = ea.wrapping_add(1);
                    bytes_left -= 1;
                }
                rs = (rs + 1) % 32;
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Byte count from XER[25..31]. Unlike stswi, the byte count NB (0..127) is read from XER[25..31]. The xenia snapshot does let nb = (ctx.xer() & 0x7F) as u32;. NB = 0 means literally zero bytes — the instruction becomes a no-op.
• Register packing identical to stswi. Bytes are pulled from successive GPRs, four bytes per register, big-endian within each register, with wraparound r31 → r0. The final partial register's unused trailing bytes are not written.
• RA0 semantics. RA = 0 selects literal zero. The instruction has no update form — RA is not modified.
• Invalid forms. AIX flags as invalid the cases where the byte-stream wraps through RA or RB while reading the source registers; xenia performs writes regardless.
• Big-endian byte ordering inside each register. Writes most-significant byte of each source GPR's low word first.
• Used for non-multiple-of-4 copies. Together with lswx, gives a way to store a runtime-determined byte count without per-byte loops. Compilers don't emit it.
• Alignment. Architecture allows arbitrary alignment; cache-inhibited storage may raise alignment exceptions on hardware.
• No CR / FPSCR effects.

Related Instructions

• lswx — symmetric load.
• stswi — sibling with byte count encoded as RB field (immediate-style).
• stmw — word-granular bulk store (no byte tail handling).
• stw, stb — scalar stores.

IBM Reference

• AIX 7.3 — stswx (Store String Word Indexed)
• PowerISA v2.07B Book II § "Load and Store String" for invalid-form rules and XER interaction.