xenia-rs/migration/project-root/ppc-manual/memory/stvxl.md

stvxl — Store Vector Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c0003ce

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvxl	stvxl	—	Store Vector Indexed LRU
stvxl128	stvxl128	—	Store Vector Indexed LRU 128

Syntax

stvxl [VS], [RA0], [RB]
stvxl128 [VS], [RA0], [RB]

Encoding

stvxl — form X

• Opcode word: 0x7c0003ce
• Primary opcode (bits 0–5): 31
• Extended opcode: 487
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvxl128 — form VX128_1

• Opcode word: 0x100003c3
• Primary opcode (bits 0–5): 4
• Extended opcode: 963
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvxl: read; stvxl128: read	Source vector register (alias for VD on stores).
RA0	stvxl: read; stvxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvxl: read; stvxl128: read	Source GPR.

Register Effects

stvxl

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvxl128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvxl

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvxl"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:199
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:79
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:813
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1970-1981

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvxl | PpcOpcode::stvxl128 => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
            // PPCBUG-511: stvxl/stvxl128 were missing invalidate_for_write.
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            let vs = if matches!(instr.opcode, PpcOpcode::stvxl128) { instr.vs128() } else { instr.rs() };
            let bytes = ctx.vr[vs].as_bytes();
            for i in 0..16 { mem.write_u8(ea + i as u32, bytes[i]); }
            ctx.pc += 4;
        }

stvxl128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvxl128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:202
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:79
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:419
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1970-1981

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvxl | PpcOpcode::stvxl128 => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
            // PPCBUG-511: stvxl/stvxl128 were missing invalidate_for_write.
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            let vs = if matches!(instr.opcode, PpcOpcode::stvxl128) { instr.vs128() } else { instr.rs() };
            let bytes = ctx.vr[vs].as_bytes();
            for i in 0..16 { mem.write_u8(ea + i as u32, bytes[i]); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Same data effect as stvx, with LRU cache hint. Writes 16 bytes from VS at EA & ~0xF. The l suffix tells the cache the line is least-recently-used — useful for streaming output (e.g. one-pass writes to a render target the producer will not re-read).
• Hint ignored under emulation. Xenia's snapshot is shared with the VMX128 variant; it implements only the data side. Hardware uses the hint to choose write-allocate vs. write-streaming behaviour.
• Alignment is forced, not checked. Low four bits of EA are masked.
• Big-endian lane layout. Lane 0 of VS lands at the aligned base; lane 15 at base+15.
• RA0 semantics. RA = 0 selects literal zero.
• No update form.
• VMX128 sibling (stvxl128). Identical semantics; alternative operand encoding addressing v0..v127 via the split-field 7-bit register index.
• Common in render-target writes. Pair with dcbz128 to allocate-and-zero, then stvxl to commit each line of a streaming output buffer; the LRU hint frees cache for the next line.

Related Instructions

• stvx, stvx128 — non-hint variants.
• lvxl, lvxl128 — symmetric LRU loads.
• stvebx, stvehx, stvewx — single-element stores.
• stvlx, stvrx — store-left / store-right unaligned ops.

IBM Reference

• AIX 7.3 — stvxl (Store Vector Indexed Last)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for stvxl128.