e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
258 lines
11 KiB
Markdown
258 lines
11 KiB
Markdown
# `stw` — Store Word
|
||
|
||
> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x90000000`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `stw` | `stw` | — | Store Word |
|
||
| `stwu` | `stwu` | — | Store Word with Update |
|
||
| `stwux` | `stwux` | — | Store Word with Update Indexed |
|
||
| `stwx` | `stwx` | — | Store Word Indexed |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
stw [RS], [d]([RA0])
|
||
stwu [RS], [d]([RA])
|
||
stwux [RS], [RA], [RB]
|
||
stwx [RS], [RA0], [RB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `stw` — form `D`
|
||
|
||
- **Opcode word:** `0x90000000`
|
||
- **Primary opcode (bits 0–5):** `36`
|
||
- **Extended opcode:** —
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT` | destination GPR (or RS when storing) |
|
||
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
|
||
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
|
||
|
||
### `stwu` — form `D`
|
||
|
||
- **Opcode word:** `0x94000000`
|
||
- **Primary opcode (bits 0–5):** `37`
|
||
- **Extended opcode:** —
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT` | destination GPR (or RS when storing) |
|
||
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
|
||
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
|
||
|
||
### `stwux` — form `X`
|
||
|
||
- **Opcode word:** `0x7c00016e`
|
||
- **Primary opcode (bits 0–5):** `31`
|
||
- **Extended opcode:** `183`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT/FRT/VRT` | destination |
|
||
| 11–15 | `RA/FRA/VRA` | source A |
|
||
| 16–20 | `RB/FRB/VRB` | source B |
|
||
| 21–30 | `XO` | extended opcode (10 bits) |
|
||
| 31 | `Rc` | record-form flag |
|
||
|
||
### `stwx` — form `X`
|
||
|
||
- **Opcode word:** `0x7c00012e`
|
||
- **Primary opcode (bits 0–5):** `31`
|
||
- **Extended opcode:** `151`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT/FRT/VRT` | destination |
|
||
| 11–15 | `RA/FRA/VRA` | source A |
|
||
| 16–20 | `RB/FRB/VRB` | source B |
|
||
| 21–30 | `XO` | extended opcode (10 bits) |
|
||
| 31 | `Rc` | record-form flag |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `RS` | stw: read; stwu: read; stwux: read; stwx: read | Source GPR (alias for RD in some stores). |
|
||
| `RA0` | stw: read; stwx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
|
||
| `d` | stw: read; stwu: read | 16-bit signed displacement (`d`) added to the base address register. |
|
||
| `RA` | stwu: read; stwu: write; stwux: read; stwux: write | Source GPR (`r0`–`r31`). |
|
||
| `RB` | stwux: read; stwx: read | Source GPR. |
|
||
|
||
## Register Effects
|
||
|
||
### `stw`
|
||
|
||
- **Reads (always):** `RS`, `RA0`, `d`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** _none_
|
||
- **Writes (conditional):** _none_
|
||
|
||
### `stwu`
|
||
|
||
- **Reads (always):** `RS`, `RA`, `d`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `RA`
|
||
- **Writes (conditional):** _none_
|
||
|
||
### `stwux`
|
||
|
||
- **Reads (always):** `RS`, `RA`, `RB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `RA`
|
||
- **Writes (conditional):** _none_
|
||
|
||
### `stwx`
|
||
|
||
- **Reads (always):** `RS`, `RA0`, `RB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** _none_
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
EA <- (RA|0) + EXTS(d)
|
||
MEM(EA, 4) <- (RS)[32:63]
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* stw RS, d(RA) */
|
||
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
|
||
uint32_t ea = (uint32_t)(base + (int64_t)(int16_t)insn.D);
|
||
mem_write_u32_be(ea, (uint32_t)r[insn.RS]);
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`stw`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stw"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:507`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L507)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:81`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L81)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:359`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L359)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1291-1299`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1291-L1299)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::stw => {
|
||
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
|
||
let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
|
||
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
|
||
if t.has_active_reservers() { t.invalidate_for_write(ea); }
|
||
}
|
||
mem.write_u32(ea, ctx.gpr[instr.rs()] as u32);
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
**`stwu`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stwu"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:543`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L543)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:81`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L81)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:360`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L360)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1300-1308`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1300-L1308)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::stwu => {
|
||
let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
|
||
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
|
||
if t.has_active_reservers() { t.invalidate_for_write(ea); }
|
||
}
|
||
mem.write_u32(ea, ctx.gpr[instr.rs()] as u32);
|
||
ctx.gpr[instr.ra()] = ea as u64;
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
**`stwux`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stwux"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:553`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L553)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:81`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L81)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:787`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L787)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1318-1326`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1318-L1326)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::stwux => {
|
||
let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
|
||
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
|
||
if t.has_active_reservers() { t.invalidate_for_write(ea); }
|
||
}
|
||
mem.write_u32(ea, ctx.gpr[instr.rs()] as u32);
|
||
ctx.gpr[instr.ra()] = ea as u64;
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
**`stwx`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stwx"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:563`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L563)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:81`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L81)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:783`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L783)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1309-1317`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1309-L1317)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::stwx => {
|
||
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
|
||
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
|
||
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
|
||
if t.has_active_reservers() { t.invalidate_for_write(ea); }
|
||
}
|
||
mem.write_u32(ea, ctx.gpr[instr.rs()] as u32);
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **Stores low 32 bits of `RS`.** Writes `(RS)[32:63]` — the low word of the 64-bit GPR — at `EA`. The xenia snapshot does `mem.write_u32(ea, ctx.gpr[instr.rs()] as u32)`. The high 32 bits are silently truncated; use [`std`](std.md) to store all 64 bits.
|
||
- **Big-endian write.** `RS[32:39]` (the most-significant byte of the low word) lands at `EA`; `RS[56:63]` at `EA+3`. On little-endian hosts the byte-swap happens at the memory boundary.
|
||
- **`RA0` (non-update forms).** `RA = 0` in `stw` and `stwx` selects literal zero. Update forms `stwu` / `stwux` invoke `RA = 0` as an invalid form. **The classic frame-allocation idiom** `stwu r1, -framesize(r1)` exploits the update form: it writes the old SP at the new SP and updates `r1` in one instruction.
|
||
- **Update-form post-write.** `stwu` / `stwux` write `EA` to `RA` after the store. Order is store-then-update, so the new `RA` value reflects the post-update address (typically the new stack-frame base).
|
||
- **No alignment requirement.** Xenon tolerates unaligned word stores. PowerISA permits implementations to raise alignment exceptions on cache-inhibited storage.
|
||
- **Cache-line behaviour.** A word store fits inside one Xenon cache line (128 B). Stores that **straddle** a line boundary touch two lines; keep words 4-byte aligned for best performance.
|
||
- **Common as pointer / ABI store.** Standard store for any `int32_t`/`uint32_t`/pointer field (Xbox 360 user pointers are 32-bit) and the workhorse of stack-frame setup.
|
||
|
||
## Related Instructions
|
||
|
||
- [`stb`](stb.md), [`sth`](sth.md), [`std`](std.md) — narrower / wider integer stores.
|
||
- [`stwbrx`](stwbrx.md) — byte-reversed word store.
|
||
- [`stwcx`](stwcx.md) — store-conditional word (the reservation pair end).
|
||
- [`lwz`](lwz.md), [`lwa`](lwa.md), [`lwarx`](lwarx.md) — corresponding loads.
|
||
- [`stmw`](stmw.md), [`stswi`](stswi.md), [`stswx`](stswx.md) — bulk stores.
|
||
- [`stfs`](stfs.md), [`stfiwx`](stfiwx.md) — FP-side equivalents.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `stw` (Store Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stw-store-word-instruction)
|
||
- [AIX 7.3 — `stwu` / `stwx` / `stwux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stwu-store-word-update-instruction)
|