xenia-rs/migration/project-root/ppc-manual/vmx/vadduwm.md

vadduwm — Vector Add Unsigned Word Modulo

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000080

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vadduwm	vadduwm	—	Vector Add Unsigned Word Modulo

Syntax

vadduwm [VD], [VA], [VB]

Encoding

vadduwm — form VX

• Opcode word: 0x10000080
• Primary opcode (bits 0–5): 4
• Extended opcode: 128
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vadduwm: read	Source A vector register.
VB	vadduwm: read	Source B vector register.
VD	vadduwm: write	Destination vector register.

Register Effects

vadduwm

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vadduwm

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vadduwm"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:402
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:90
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:448
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2396-2403

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vadduwm => {
            let a = ctx.vr[instr.ra()].as_u32x4();
            let b = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = a[i].wrapping_add(b[i]); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Four 32-bit word lanes. VD[i] = (VA[i] + VB[i]) mod 2^32 for i = 0..3. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• Modulo wrap, not saturating. Carry is dropped; VSCR[SAT] is not touched. Sign-agnostic — bit-pattern-identical for signed int32 and unsigned u32 modulo addition.
• Multi-precision idiom. Pair with vaddcuw to recover the per-lane carry, then vsldoi the carry one word left and feed it back into another vadduwm to chain a 128-bit add.
• No XER, no NJ involvement.
• Aliasing legal. vadduwm v3, v3, v4.
• No VMX128 sibling in the vadduwm mnemonic specifically; vaddfp128 covers the float case, but integer-modulo-word stays VMX-only.
• Common usage. RGBA8 packed-pixel sums; per-tile counters; BigInt limbs.

Related Instructions

• vaddcuw — produces the per-lane carry that vadduwm discards.
• vadduws, vaddsws — unsigned / signed saturating add at the same width.
• vaddubm, vadduhm — modulo add at byte / half width.
• vsubuwm — the matching modulo subtract.
• vsldoi — used to align carries during multi-precision chains.

IBM Reference

• AIX 7.3 — vadduwm (Vector Add Unsigned Word Modulo)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Integer Arithmetic & multi-precision idiom