fabi/xenia-rs
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
e6d43a23ac393004d2e5adf2f0395fd0b5e6448b
xenia-rs/migration/project-root/ppc-manual/vmx/vandc.md
MechaCat02 e6d43a23ac chore: add migration/ bundle for cross-machine setup 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-10 21:38:38 +02:00

182 lines
7.2 KiB
Markdown
Raw Blame History

This file contains ambiguous Unicode characters
This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.
# `vandc` — Vector Logical AND with Complement
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000444`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vandc` | `vandc` | — | Vector Logical AND with Complement |
| `vandc128` | `vandc128` | — | Vector128 Logical AND with Complement |
## Syntax
```asm
vandc [VD], [VA], [VB]
vandc128 [VD], [VA], [VB]
```
## Encoding
### `vandc` — form `VX`
- **Opcode word:** `0x10000444`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `1092`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |
### `vandc128` — form `VX128`
- **Opcode word:** `0x14000250`
- **Primary opcode (bits 0–5):** `5`
- **Extended opcode:** `592`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4 or 5) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22 | `—` | reserved |
| 23–25 | `VC` | optional VC / XO sub-field |
| 26 | `VA128h` | source A middle bit |
| 27 | `—` | reserved |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vandc: read; vandc128: read | Source A vector register. |
| `VB` | vandc: read; vandc128: read | Source B vector register. |
| `VD` | vandc: write; vandc128: write | Destination vector register. |
## Register Effects
### `vandc`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `vandc128`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vandc`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vandc"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:436`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L436)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:91`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L91)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:526`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L526)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2217-2225`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2217-L2225)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vandc | PpcOpcode::vandc128 => {
let (va, vb, vd) = vmx_reg_triple(instr);
let a = ctx.vr[va].as_u32x4();
let b = ctx.vr[vb].as_u32x4();
let mut r = [0u32; 4];
for i in 0..4 { r[i] = a[i] & !b[i]; }
ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
ctx.pc += 4;
}
```
</details>
**`vandc128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vandc128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:439`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L439)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:91`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L91)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:621`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L621)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2217-2225`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2217-L2225)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vandc | PpcOpcode::vandc128 => {
let (va, vb, vd) = vmx_reg_triple(instr);
let a = ctx.vr[va].as_u32x4();
let b = ctx.vr[vb].as_u32x4();
let mut r = [0u32; 4];
for i in 0..4 { r[i] = a[i] & !b[i]; }
ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
ctx.pc += 4;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Bitwise AND-with-complement of the full 128 bits.** `VD = VA & ~VB`. Lane width is irrelevant — the operation is bit-for-bit. Order matters: `vandc VA, VB` is *not* the same as `vandc VB, VA`.
- **Standard "clear bits in mask" idiom.** Drop bits selected by the mask in `VB`: `vandc VD, VD, vMask`. Equivalent to `VD &= ~vMask`. Cheaper than synthesising the complement first with [`vnor`](vnor.md) and then ANDing.
- **Compare → mask → mask-out idiom.** A compare produces per-lane all-ones; pair with `vandc` to keep only the lanes where the compare was *false*. The complement avoids an extra [`vnor`](vnor.md) or `vxor` with all-ones.
- **No flags, no exceptions, no `VSCR` interaction.**
- **Aliasing legal.** `vandc VD, VD, VD` clears `VD` (`x & ~x = 0`).
- **VMX128 sibling (`vandc128`).** Identical semantics with the extended 128-register encoding; xenia reuses one match arm.
## Related Instructions
- [`vand`](vand.md) — the un-complemented sibling.
- [`vor`](vor.md), [`vxor`](vxor.md), [`vnor`](vnor.md) — the rest of the bitwise family.
- [`vsel`](vsel.md) — bitwise select using a third register; useful when the "false" branch is non-zero.
- [`vcmpequb`](vcmpequb.md) and other compares — natural mask producers.
## IBM Reference
- [AIX 7.3 — `vandc` (Vector Logical AND with Complement)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vandc-vector-logical-complement-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Logical Operations](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
Reference in New Issue View Git Blame Copy Permalink