xenia-rs/migration/project-root/ppc-manual/vmx/vavgsb.md

vavgsb — Vector Average Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000502

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vavgsb	vavgsb	—	Vector Average Signed Byte

Syntax

vavgsb [VD], [VA], [VB]

Encoding

vavgsb — form VX

• Opcode word: 0x10000502
• Primary opcode (bits 0–5): 4
• Extended opcode: 1282
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vavgsb: read	Source A vector register.
VB	vavgsb: read	Source B vector register.
VD	vavgsb: write	Destination vector register.

Register Effects

vavgsb

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vavgsb

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vavgsb"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:443
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:92
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:533
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3410-3417

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vavgsb => {
            let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i8x16(ctx.vr[instr.rb()]);
            let mut r = [0i8; 16];
            for i in 0..16 { r[i] = crate::vmx::avg_i8(a[i], b[i]); }
            ctx.vr[instr.rd()] = crate::vmx::from_i8x16(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Sixteen signed-byte rounding averages. Each VD[i] = (VA[i] + VB[i] + 1) >> 1, performed in arithmetic wider than 8 bits (so the +1 cannot overflow). The result is then truncated back to int8 — saturation never triggers because the average of two int8 values fits in int8. Rounding is "round half up toward +∞".
• Big-endian byte lanes. Lane 0 is the most-significant byte after stvx.
• No VSCR[SAT] impact. Mathematical impossibility — (a + b + 1) / 2 for a, b ∈ [-128, 127] always lies in [-128, 127]. Xenia's crate::vmx::avg_i8 (crates/xenia-cpu/src/vmx.rs) widens to i16 before the add.
• No XER side effects.
• Common usage. Filtering / decimation passes, motion-compensation half-pel interpolation in older video codecs (the rounding-up bias matches MPEG/H.263 averaging conventions).
• Aliasing legal. vavgsb v3, v3, v4 is a typical lowpass-step idiom.
• No VMX128 sibling.

Related Instructions

• vavgub — same width, unsigned rounding average.
• vavgsh, vavgsw — signed rounding average at half / word width.
• vaddubm, vaddsbs — addition variants without the rounding-divide step.
• vsububm — modulo subtract; needed for differential before averaging.

IBM Reference

• AIX 7.3 — vavgsb (Vector Average Signed Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Average Instructions