xenia-rs/migration/project-root/ppc-manual/vmx/vavguw.md

vavguw — Vector Average Unsigned Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000482

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vavguw	vavguw	—	Vector Average Unsigned Word

Syntax

vavguw [VD], [VA], [VB]

Encoding

vavguw — form VX

• Opcode word: 0x10000482
• Primary opcode (bits 0–5): 4
• Extended opcode: 1154
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vavguw: read	Source A vector register.
VB	vavguw: read	Source B vector register.
VD	vavguw: write	Destination vector register.

Register Effects

vavguw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vavguw

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vavguw"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:482
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:92
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:530
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3434-3441

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vavguw => {
            let a = ctx.vr[instr.ra()].as_u32x4();
            let b = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = crate::vmx::avg_u32(a[i], b[i]); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Four unsigned-word rounding averages. Each VD[i] = (VA[i] + VB[i] + 1) >> 1, computed in 64-bit arithmetic to avoid intermediate overflow, then truncated to u32. Rounding is half-up.
• Big-endian word lanes. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• No VSCR[SAT] impact. The result always fits in u32. Xenia uses crate::vmx::avg_u32 (crates/xenia-cpu/src/vmx.rs).
• No SSE2 direct equivalent. SSE2 only provides _mm_avg_epu8 and _mm_avg_epu16; on x86 hosts xenia has to widen to 64-bit and do the average manually.
• Common usage. Per-tile counters; midpoint of two 32-bit packed values.
• Aliasing legal.
• No VMX128 sibling.

Related Instructions

• vavgsw — same width, signed rounding average.
• vavgub, vavguh — unsigned rounding average at byte / half width.
• vadduwm, vadduws — addition variants without the divide step.
• vsubuwm — modulo subtract; difference before averaging.

IBM Reference

• AIX 7.3 — vavguw (Vector Average Unsigned Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Average Instructions