xenia-rs/migration/project-root/ppc-manual/vmx/vcfsx.md

vcfsx — Vector Convert from Signed Fixed-Point Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000034a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcfs	vcfsx	—	Vector Convert from Signed Fixed-Point Word

Syntax

vcfsx [VD], [VB], [UIMM]

Encoding

vcfsx — form VX

• Opcode word: 0x1000034a
• Primary opcode (bits 0–5): 4
• Extended opcode: 842
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	vcfsx: read	Source B vector register.
UIMM	vcfsx: read	16-bit unsigned immediate. Zero-extended.
VD	vcfsx: write	Destination vector register.

Register Effects

vcfsx

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcfsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vcfsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:500
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:93
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:509
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4306-4313

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vcfsx => {
            let uimm = (instr.raw >> 16) & 0x1F;
            let b = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = crate::vmx::cvt_i32_to_f32(b[i], uimm); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Convert signed-Q int32 lane to binary32. For each of the four word lanes, VD[i] = (float)VB[i] / 2^UIMM, where UIMM is the 5-bit immediate at bits 11..15 of the instruction. UIMM ranges 0..31; UIMM=0 is plain integer-to-float.
• Big-endian word lanes. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• Use case. Q-format fixed-point (Qm.n) → IEEE float in one instruction. UIMM gives the fractional bit count, so vcfsx vD, vB, 16 interprets each lane as Q15.16.
• Inexact rounding. Values whose magnitude exceeds 2^24 lose mantissa precision (only 24 bits in binary32's significand). The default rounding mode is round-to-nearest-even; VMX has no per-instruction rounding control.
• VSCR[NJ] (flush-denormals) affects the output if the scaled value is sub-normal. Xenia's crate::vmx::cvt_i32_to_f32 honours this via the architectural VSCR[NJ] snapshot.
• No VSCR[SAT] or XER changes, no exceptions raised.
• No VMX128 sibling.
• Round-trip caveat. vctsxs (the inverse) saturates instead of wrapping, so a vcfsx/vctsxs round-trip is not identity for values outside the signed-int32 representable range — important for fixed-point interpolation kernels.

Related Instructions

• vcfux — same shape, unsigned source.
• vctsxs — inverse: float → signed-Q int32 with saturation.
• vctuxs — inverse: float → unsigned-Q uint32 with saturation.
• vrfin, vrfiz — float-to-integer rounding modes when no Q-format scale is needed.

IBM Reference

• AIX 7.3 — vcfsx (Vector Convert from Signed Fixed-Point Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Conversion Instructions