xenia-rs/migration/project-root/ppc-manual/vmx/vctsxs.md

vctsxs — Vector Convert to Signed Fixed-Point Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x100003ca

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vctsxs	vctsxs	—	Vector Convert to Signed Fixed-Point Word Saturate

Syntax

vctsxs [VD], [VB], [UIMM]

Encoding

vctsxs — form VX

• Opcode word: 0x100003ca
• Primary opcode (bits 0–5): 4
• Extended opcode: 970
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	vctsxs: read	Source B vector register.
UIMM	vctsxs: read	16-bit unsigned immediate. Zero-extended.
VD	vctsxs: write	Destination vector register.
VSCR	vctsxs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vctsxs

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vctsxs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vctsxs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vctsxs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:536
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:98
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:517
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4281-4292

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vctsxs => {
            let uimm = (instr.raw >> 16) & 0x1F;
            let b = ctx.vr[instr.rb()].as_f32x4();
            let mut r = [0i32; 4]; let mut sat = false;
            for i in 0..4 {
                let (v, s) = crate::vmx::cvt_f32_to_i32_sat(b[i], uimm);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Convert IEEE float lane to signed-Q int32, saturating. For each of the four word lanes, VD[i] = clamp(round_toward_zero(VB[i] * 2^UIMM), INT32_MIN, INT32_MAX). The 5-bit UIMM (bits 11..15) gives the Q-format fractional shift, in 0..31.
• Saturating, not wrapping. Out-of-range floats clamp to INT32_MIN (negative overflow) or INT32_MAX (positive overflow) — not the wrap-around behaviour of x86 cvttps2dq (which produces 0x80000000 on overflow regardless of sign). Xenia's crate::vmx::cvt_f32_to_i32_sat (crates/xenia-cpu/src/vmx.rs) handles the difference.
• NaN → 0. A NaN input becomes 0 in the output lane and stickies VSCR[SAT]. (Many references state "NaN → INT32_MIN"; verify against vmx.rs for the canonical xenia behaviour, which differs from POWER ISA wording.)
• VSCR[SAT] is sticky-set if any lane saturates (overflow or NaN). Cleared only by mtvscr.
• Rounding is truncate-toward-zero. Always; no per-instruction rounding control.
• VSCR[NJ] flushes denormal inputs to zero before scaling (Xenon default).
• Big-endian word lanes. Lane 0 is the most-significant word.
• No XER changes, no traps.
• No VMX128 sibling.
• Inverse of vcfsx, but the inverse direction saturates rather than wraps — round-trips lose the magnitude of out-of-range values.

Related Instructions

• vctuxs — same shape, unsigned destination.
• vcfsx, vcfux — inverse direction (int → float with Q-shift).
• vrfin, vrfip, vrfim, vrfiz — float-to-float rounding modes (round-to-nearest, up, down, toward-zero) when staying in float.
• mtvscr / mfvscr — read or clear VSCR[SAT].

IBM Reference

• AIX 7.3 — vctsxs (Vector Convert to Signed Fixed-Point Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Conversion Instructions