xenia-rs/migration/project-root/ppc-manual/vmx/vexptefp.md

# `vexptefp` — Vector 2 Raised to the Exponent Estimate Floating Point

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000018a`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vexptefp` | `vexptefp` | — | Vector 2 Raised to the Exponent Estimate Floating Point |
| `vexptefp128` | `vexptefp128` | — | Vector128 Log2 Estimate Floating Point |

## Syntax

```asm
vexptefp [VD], [VB]
vexptefp128 [VD], [VB]
```

## Encoding

### `vexptefp` — form `VX`

- **Opcode word:** `0x1000018a`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `394`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

### `vexptefp128` — form `VX128_3`

- **Opcode word:** `0x180006b0`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `1712`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VB` | vexptefp: read; vexptefp128: read | Source B vector register. |
| `VD` | vexptefp: write; vexptefp128: write | Destination vector register. |

## Register Effects

### `vexptefp`

- **Reads (always):** `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

### `vexptefp128`

- **Reads (always):** `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vexptefp`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vexptefp"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:766`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L766)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:99`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L99)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:469`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L469)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4367-4376`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4367-L4376)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vexptefp | PpcOpcode::vexptefp128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vexptefp128);
            let (rb, rd) = if is_128 { (instr.vb128(), instr.vd128()) }
                           else { (instr.rb(), instr.rd()) };
            let b = ctx.vr[rb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = b[i].exp2(); }
            ctx.vr[rd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

**`vexptefp128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vexptefp128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:769`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L769)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:99`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L99)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:666`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L666)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4367-4376`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4367-L4376)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vexptefp | PpcOpcode::vexptefp128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vexptefp128);
            let (rb, rd) = if is_128 { (instr.vb128(), instr.vd128()) }
                           else { (instr.rb(), instr.rd()) };
            let b = ctx.vr[rb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = b[i].exp2(); }
            ctx.vr[rd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Per-lane base-2 exponent.** Each of the four word lanes computes `VD[i] = 2^VB[i]` in `binary32`. **Note:** the IBM manual specifies a low-precision estimate (≤ 1/16 ULP relative error). Xenia uses Rust's `f32::exp2`, which is full-precision — programs that depend on hardware-quality estimation may observe small numerical differences.
- **Use `vlogefp` for the inverse.** The natural pair is `vexptefp(vlogefp(x)) = x` for positive finite `x`, modulo each estimate's error budget.
- **Big-endian word lanes.** Lane 0 is the most-significant word.
- **NaN, ±∞.** `2^NaN = NaN`; `2^(+∞) = +∞`; `2^(-∞) = +0`. Subnormal results may be flushed to `±0` if `VSCR[NJ] = 1` (Xenon default).
- **No exception, no `VSCR[SAT]` change, no XER change.**
- **VMX128 sibling (`vexptefp128`).** Identical semantics with the extended encoding.
- **Build natural exp / log via change-of-base.** `e^x = 2^(x * log2(e))`, so combine `vmaddfp` (multiply-by-constant) with `vexptefp`.

## Related Instructions

- [`vlogefp`](vlogefp.md) — base-2 logarithm (the inverse).
- [`vrefp`](vrefp.md) — reciprocal estimate.
- [`vrsqrtefp`](vrsqrtefp.md) — reciprocal-square-root estimate.
- [`vmaddfp`](vmaddfp.md) — fused multiply-add for change-of-base scaling.
- [`vmulfp`](vmulfp.md) — float multiply (xenia helper).

## IBM Reference

- [AIX 7.3 — `vexptefp` (Vector 2 Raised to the Exponent Estimate Floating Point)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vexptefp-vector-2-raised-exponent-estimate-floating-point-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Estimate Instructions](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)