xenia-rs/migration/project-root/ppc-manual/vmx/vmsumshs.md

vmsumshs — Vector Multiply-Sum Signed Half Word Saturate

Category: VMX (Altivec) · Form: VA · Opcode: 0x10000029

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmsumshs	vmsumshs	—	Vector Multiply-Sum Signed Half Word Saturate

Syntax

vmsumshs [VD], [VA], [VB], [VC]

Encoding

vmsumshs — form VA

• Opcode word: 0x10000029
• Primary opcode (bits 0–5): 4
• Extended opcode: 41
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

Operands

Field	Role	Description
VA	vmsumshs: read	Source A vector register.
VB	vmsumshs: read	Source B vector register.
VC	vmsumshs: read	Source C vector register / 3-bit selector.
VD	vmsumshs: write	Destination vector register.
VSCR	vmsumshs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vmsumshs

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vmsumshs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmsumshs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmsumshs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1047
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:107
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:584
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3639-3655

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmsumshs => {
            let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
            let c = crate::vmx::as_i32x4(ctx.vr[instr.rc()]);
            let mut r = [0i32; 4]; let mut sat = false;
            for i in 0..4 {
                // Running-sum saturation: accumulate in i64, clamp once at end.
                let s = (a[2*i] as i64 * b[2*i] as i64)
                    + (a[2*i+1] as i64 * b[2*i+1] as i64)
                    + c[i] as i64;
                let (v, o) = crate::vmx::sat_i64_to_i32(s);
                r[i] = v; sat |= o;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Signed half-word multiply-sum, saturating. Per word lane:

  VD[i] = clamp(VC[i] + int16(VA[2*i]) * int16(VB[2*i])
                       + int16(VA[2*i+1]) * int16(VB[2*i+1]), INT32_MIN, INT32_MAX)
  

  Two signed-half × signed-half products plus a signed-word accumulator, clamped to int32.
• Wide-then-clamp ordering. Xenia accumulates into i64 first and clamps the final sum to int32, exactly matching the IBM specification (crates/xenia-cpu/src/vmx.rs). This avoids spurious mid-sum saturation that would happen if the products were clamped individually.
• VSCR[SAT] is sticky-set if any of the four lane sums saturates. Cleared only via mtvscr.
• Big-endian half lanes. Lane 0 is the most-significant half.
• No XER, no exceptions.
• Aliasing legal.
• No VMX128 sibling.
• Common usage. High-precision dot products, audio FIR taps with overflow detection, signed-pixel filter convolution.

Related Instructions

• vmsumshm — same shape, modulo (no clamp, no SAT flag).
• vmsumuhs — unsigned half multiply-sum, saturating.
• vmsummbm, vmsumubm — multiply-sum at byte width.
• vaddsws — saturating word add for further accumulation.
• mtvscr / mfvscr — read or clear VSCR[SAT].

IBM Reference

• AIX 7.3 — vmsumshs (Vector Multiply-Sum Signed Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family