xenia-rs/migration/project-root/ppc-manual/vmx/vmsumubm.md

# `vmsumubm` — Vector Multiply-Sum Unsigned Byte Modulo

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000024`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmsumubm` | `vmsumubm` | — | Vector Multiply-Sum Unsigned Byte Modulo |

## Syntax

```asm
vmsumubm [VD], [VA], [VB], [VC]
```

## Encoding

### `vmsumubm` — form `VA`

- **Opcode word:** `0x10000024`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `36`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmsumubm: read | Source A vector register. |
| `VB` | vmsumubm: read | Source B vector register. |
| `VC` | vmsumubm: read | Source C vector register / 3-bit selector. |
| `VD` | vmsumubm: write | Destination vector register. |

## Register Effects

### `vmsumubm`

- **Reads (always):** `VA`, `VB`, `VC`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmsumubm`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsumubm"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1052`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1052)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:107`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L107)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:579`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L579)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3564-3578`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3564-L3578)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmsumubm => {
            let a = ctx.vr[instr.ra()].as_bytes();
            let b = ctx.vr[instr.rb()].as_bytes();
            let c = ctx.vr[instr.rc()].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 {
                let mut s = c[i];
                for j in 0..4 {
                    s = s.wrapping_add(a[4*i+j] as u32 * b[4*i+j] as u32);
                }
                r[i] = s;
            }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Unsigned byte multiply-sum, modulo.** Per word lane:
  ```
  VD[i] = (VC[i] + Σ_{j=0..3} uint8(VA[4*i + j]) * uint8(VB[4*i + j])) mod 2^32
  ```
  Four unsigned-byte × unsigned-byte products and an unsigned-word accumulator from `VC`, summed into one unsigned word per lane.
- **Modulo wrap, never saturates.** **`VSCR[SAT]` is not touched** — wraparound silently.
- **Big-endian byte lanes.** Lane 0 is the most-significant byte; output word `i` consumes bytes `4*i .. 4*i+3`.
- **No XER, no exceptions.**
- **Aliasing legal.**
- **No VMX128 sibling.**
- **Common usage.** Pixel-component dot products (RGBA × weights packed as bytes); 4-tap unsigned convolution; per-pixel "intensity sum" where the weights are byte-quantised.

## Related Instructions

- [`vmsummbm`](vmsummbm.md) — same shape, signed × unsigned (mixed-sign).
- [`vmsumuhm`](vmsumuhm.md) / [`vmsumuhs`](vmsumuhs.md) — unsigned half multiply-sum (modulo / saturate).
- [`vmsumshm`](vmsumshm.md) / [`vmsumshs`](vmsumshs.md) — signed half multiply-sum.
- [`vsum4ubs`](vsum4ubs.md) — pure horizontal sum of bytes into words.

## IBM Reference

- [AIX 7.3 — `vmsumubm` (Vector Multiply-Sum Unsigned Byte Modulo)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmsumubm-vector-multiply-sum-unsigned-byte-modulo-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)