xenia-rs/migration/project-root/ppc-manual/vmx/vpkpx.md

vpkpx — Vector Pack Pixel

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000030e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vpkp	vpkpx	—	Vector Pack Pixel

Syntax

vpkpx [VD], [VA], [VB]

Encoding

vpkpx — form VX

• Opcode word: 0x1000030e
• Primary opcode (bits 0–5): 4
• Extended opcode: 782
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vpkpx: read	Source A vector register.
VB	vpkpx: read	Source B vector register.
VD	vpkpx: write	Destination vector register.

Register Effects

vpkpx

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vpkpx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkpx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1810
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:113
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:504
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4123-4131

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkpx => {
            let a = ctx.vr[instr.ra()].as_u32x4();
            let b = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0u16; 8];
            for i in 0..4 { r[i] = crate::vmx::pack_pixel_555(a[i]); }
            for i in 0..4 { r[4 + i] = crate::vmx::pack_pixel_555(b[i]); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Pack 4×4 pixel words → 8×16-bit 1-5-5-5 pixels. For each 32-bit word lane, three bit-fields are sampled and concatenated into a 16-bit 1.5.5.5 (A.R.G.B) format, losing precision but not saturating.
• Bit-layout of each output half-word. Bit 0 of the output = bit 7 of the source byte (alpha); the next 5 bits come from the red channel's top 5 bits (bits 8..12 of the source word); then 5 bits of green (bits 16..20); then 5 bits of blue (bits 24..28). Xenia's helper is vmx::pack_pixel_555 (in crates/xenia-cpu/src/vmx.rs).
• No saturation / no rounding. The op truncates the lower bits of each channel; VSCR[SAT] is not affected.
• Big-endian lane order. VA's 4 words produce the first 4 output half-words (VD.h[0..3]); VB's 4 words fill VD.h[4..7].
• Paired with vupkhpx / vupklpx — these unpack a 1-5-5-5 pixel back into a word-lane 0x00RRGGBB-like form for further arithmetic.
• No Rc, no XER. No VMX128 sibling — game code that needs 555-pixel packing on Xenon either uses the scalar path or runs into the vpkd3d128 family for richer D3D formats.

Related Instructions

• vupkhpx, vupklpx — the inverse unpacks.
• vpkuhum, vpkuhus, vpkuwum, vpkuwus — lane-halving packs (unsigned modulo / saturating).
• vpkshss, vpkshus, vpkswss, vpkswus — signed-input saturating packs.
• vpkd3d128 — VMX128-exclusive D3D-format pack (richer pixel formats than 1-5-5-5).

IBM Reference

• AIX 7.3 — vpkpx (Vector Pack Pixel32)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting