xenia-rs/migration/project-root/ppc-manual/vmx/vpkuwus.md

# `vpkuwus` — Vector Pack Unsigned Word Unsigned Saturate

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x100000ce`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vpkuwus` | `vpkuwus` | — | Vector Pack Unsigned Word Unsigned Saturate |
| `vpkuwus128` | `vpkuwus128` | — | Vector128 Pack Unsigned Word Unsigned Saturate |

## Syntax

```asm
vpkuwus [VD], [VA], [VB]
vpkuwus128 [VD], [VA], [VB]
```

## Encoding

### `vpkuwus` — form `VX`

- **Opcode word:** `0x100000ce`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `206`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

### `vpkuwus128` — form `VX128`

- **Opcode word:** `0x140003c0`
- **Primary opcode (bits 0–5):** `5`
- **Extended opcode:** `960`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4 or 5) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22 | `—` | reserved |
| 23–25 | `VC` | optional VC / XO sub-field |
| 26 | `VA128h` | source A middle bit |
| 27 | `—` | reserved |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vpkuwus: read; vpkuwus128: read | Source A vector register. |
| `VB` | vpkuwus: read; vpkuwus128: read | Source B vector register. |
| `VD` | vpkuwus: write; vpkuwus128: write | Destination vector register. |
| `VSCR` | vpkuwus: write; vpkuwus128: write | Vector Status and Control Register (NJ/SAT bits). |

## Register Effects

### `vpkuwus`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_

### `vpkuwus128`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_

## Status-Register Effects

- `vpkuwus`: **VSCR[SAT]** may be stickied on saturating vector operations.
- `vpkuwus128`: **VSCR[SAT]** may be stickied on saturating vector operations.

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vpkuwus`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkuwus"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1995`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1995)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:116`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L116)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:453`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L453)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4083-4095`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4083-L4095)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vpkuwus | PpcOpcode::vpkuwus128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkuwus128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = ctx.vr[ra].as_u32x4();
            let b = ctx.vr[rb].as_u32x4();
            let mut r = [0u16; 8]; let mut sat = false;
            for i in 0..4 { let (v, s) = crate::vmx::sat_u32_to_u16(a[i]); r[i] = v; sat |= s; }
            for i in 0..4 { let (v, s) = crate::vmx::sat_u32_to_u16(b[i]); r[4 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }
```
</details>

**`vpkuwus128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkuwus128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1998`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1998)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:116`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L116)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:632`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L632)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4083-4095`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4083-L4095)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vpkuwus | PpcOpcode::vpkuwus128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkuwus128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = ctx.vr[ra].as_u32x4();
            let b = ctx.vr[rb].as_u32x4();
            let mut r = [0u16; 8]; let mut sat = false;
            for i in 0..4 { let (v, s) = crate::vmx::sat_u32_to_u16(a[i]); r[i] = v; sat |= s; }
            for i in 0..4 { let (v, s) = crate::vmx::sat_u32_to_u16(b[i]); r[4 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Unsigned word → unsigned half-word saturating pack.** Each of the 8 input word lanes (interpreted as `uint32`) is clamped to `[0, 65535]`. Overflow sticky-sets `VSCR[SAT]`.
- **Lane-count doubling.** 8 word lanes → 8 half-word lanes; `VA` then `VB`.
- **Pair with [`vpkuwum`](vpkuwum.md)** when a modulo wrap is required.
- **`VSCR[SAT]` is sticky.**
- **No `Rc`, no XER.**
- **VMX128 sibling [`vpkuwus128`](vpkuwus128.md).**

## Related Instructions

- [`vpkuwum`](vpkuwum.md) — modulo counterpart.
- [`vpkswus`](vpkswus.md), [`vpkswss`](vpkswss.md) — signed-word input.
- [`vpkuhus`](vpkuhus.md) — half-word → byte saturating pack.
- [`vupkhsh`](vupkhsh.md), [`vupklsh`](vupklsh.md) — inverse unpack (sign-extending).
- [`vperm`](vperm.md) — irregular pack.

## IBM Reference

- [AIX 7.3 — `vpkuwus` (Vector Pack Unsigned Word Unsigned Saturate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vpkuwus-vector-pack-unsigned-word-unsigned-saturate-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)