xenia-rs/migration/project-root/ppc-manual/vmx/vrefp.md

# `vrefp` — Vector Reciprocal Estimate Floating Point

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000010a`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vrefp` | `vrefp` | — | Vector Reciprocal Estimate Floating Point |
| `vrefp128` | `vrefp128` | — | Vector128 Reciprocal Estimate Floating Point |

## Syntax

```asm
vrefp [VD], [VB]
vrefp128 [VD], [VB]
```

## Encoding

### `vrefp` — form `VX`

- **Opcode word:** `0x1000010a`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `266`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

### `vrefp128` — form `VX128_3`

- **Opcode word:** `0x18000630`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `1584`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VB` | vrefp: read; vrefp128: read | Source B vector register. |
| `VD` | vrefp: write; vrefp128: write | Destination vector register. |

## Register Effects

### `vrefp`

- **Reads (always):** `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

### `vrefp128`

- **Reads (always):** `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vrefp`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vrefp"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1227`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1227)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:117`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L117)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:457`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L457)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2153-2161`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2153-L2161)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vrefp | PpcOpcode::vrefp128 => {
            let vb = if matches!(instr.opcode, PpcOpcode::vrefp128) { instr.vb128() } else { instr.rb() };
            let vd = if matches!(instr.opcode, PpcOpcode::vrefp128) { instr.vd128() } else { instr.rd() };
            let b = ctx.vr[vb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = 1.0 / b[i]; }
            ctx.vr[vd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

**`vrefp128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vrefp128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1230`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1230)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:117`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L117)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:664`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L664)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2153-2161`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2153-L2161)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vrefp | PpcOpcode::vrefp128 => {
            let vb = if matches!(instr.opcode, PpcOpcode::vrefp128) { instr.vb128() } else { instr.rb() };
            let vd = if matches!(instr.opcode, PpcOpcode::vrefp128) { instr.vd128() } else { instr.rd() };
            let b = ctx.vr[vb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = 1.0 / b[i]; }
            ctx.vr[vd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Lane-wise reciprocal *estimate*.** Each 32-bit float lane of `VB` is approximated by `1.0 / VB[i]`. The PowerPC spec permits an **estimate** accurate to about 1/4096 (≈12 bits); xenia-rs produces the *exact* IEEE-754 reciprocal by dividing, trading accuracy for simplicity. Game code that cares about bit-reproducible behaviour should Newton-iterate with [`vnmsubfp`](vnmsubfp.md) regardless of which backend computes the seed.
- **Standard Newton iteration.** `x₁ = x₀ * (2 − VB * x₀)`, expressible as `vnmsubfp x₁, x₀, VB, 2.0f` followed by `vmaddfp x₁, x₀, x₁, 0.0f` (or similar). One iteration roughly doubles the valid bit count.
- **IEEE-754 binary32 lanes; `VSCR[NJ]` honoured** (denormals flush to zero when `NJ = 1`).
- **No VSCR[SAT] update, no FPSCR update, no exception.** Division by zero yields ±∞; division of zero yields ±∞ too (same sign convention).
- **Big-endian lane indexing.**
- **VMX128 sibling [`vrefp128`](vrefp128.md).**

## Related Instructions

- [`vrsqrtefp`](vrsqrtefp.md) — reciprocal *square root* estimate, used with the same Newton scheme.
- [`vmaddfp`](vmaddfp.md), [`vnmsubfp`](vnmsubfp.md) — the building blocks of the Newton iteration.
- [`vexptefp`](vexptefp.md), [`vlogefp`](vlogefp.md) — other "estimate"-style transcendentals.
- [`vaddfp`](vaddfp.md), [`vsubfp`](vsubfp.md) — the float add/sub.

## IBM Reference

- [AIX 7.3 — `vrefp` (Vector Reciprocal Estimate Floating Point)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vrefp-vector-reciprocal-estimate-floating-point-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)