e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
129 lines
5.0 KiB
Markdown
129 lines
5.0 KiB
Markdown
# `vsl` — Vector Shift Left
|
||
|
||
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x100001c4`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `vsl` | `vsl` | — | Vector Shift Left |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
vsl [VD], [VA], [VB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `vsl` — form `VX`
|
||
|
||
- **Opcode word:** `0x100001c4`
|
||
- **Primary opcode (bits 0–5):** `4`
|
||
- **Extended opcode:** `452`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4) |
|
||
| 6–10 | `VRT/VD` | destination vector register |
|
||
| 11–15 | `VRA/VA` | source A vector register |
|
||
| 16–20 | `VRB/VB` | source B vector register |
|
||
| 21–31 | `XO` | extended opcode (11 bits) |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `VA` | vsl: read | Source A vector register. |
|
||
| `VB` | vsl: read | Source B vector register. |
|
||
| `VD` | vsl: write | Destination vector register. |
|
||
|
||
## Register Effects
|
||
|
||
### `vsl`
|
||
|
||
- **Reads (always):** `VA`, `VB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
; Pseudocode derives directly from the xenia-rs interpreter
|
||
; arm (see Implementation References). Operation semantics:
|
||
; - Read source operands from the fields listed under Operands.
|
||
; - Apply the arithmetic / logical / memory action described
|
||
; in the Description field above.
|
||
; - Write results to the destination register(s); update any
|
||
; status bits enumerated under Status-Register Effects.
|
||
; Consult the IBM AIX reference link under IBM Reference for
|
||
; canonical PPC-style pseudocode where xenia's expression is
|
||
; terse.
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* C translation: the xenia-rs interpreter arm below in */
|
||
/* Implementation References is the authoritative semantic */
|
||
/* snapshot. Translate it line-by-line: */
|
||
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
|
||
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
|
||
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
|
||
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`vsl`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsl"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1402`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1402)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:122`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L122)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:472`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L472)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3920-3926`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3920-L3926)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::vsl => {
|
||
let a = u128::from_be_bytes(ctx.vr[instr.ra()].as_bytes());
|
||
let shift = (ctx.vr[instr.rb()].as_bytes()[15] & 7) as u32;
|
||
let r = if shift == 0 { a } else { a << shift };
|
||
ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(r.to_be_bytes());
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **Whole-register bit shift-left.** The 128-bit value `VA` is shifted left by `N` bits, where `N = VB.b[15] & 7` — i.e. the low 3 bits of the **last** (least-significant) byte of `VB`. Bits shifted out the top are discarded; zero-fill on the right.
|
||
- **Shift count constraint.** The ISA requires the same 3-bit shift count in all 16 bytes of `VB`; behaviour is undefined otherwise (xenia-rs reads only byte 15 as above). Compilers guarantee this by splatting the shift count first.
|
||
- **Combine with [`vslo`](vslo.md) for up to 127-bit shifts.** `vslo` handles the byte-granular component; `vsl` picks up the remaining 0..7 bits. The canonical 128-bit shift-left is `vslo` followed by `vsl`.
|
||
- **Big-endian.** "Left" means toward the MSB end of the register.
|
||
- **No flags, no VSCR.**
|
||
- **No VMX128 sibling.**
|
||
|
||
## Related Instructions
|
||
|
||
- [`vslo`](vslo.md) — whole-register shift-left by *octets* (bytes).
|
||
- [`vsr`](vsr.md), [`vsro`](vsro.md) — the right-shift counterparts.
|
||
- [`vsldoi`](vsldoi.md) — static-immediate byte shift of `VA ‖ VB`.
|
||
- [`vslb`](vslb.md), [`vslh`](vslh.md), [`vslw`](vslw.md) — per-lane logical shifts.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `vsl` (Vector Shift Left)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsl-vector-shift-left-instruction)
|
||
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
|