xenia-rs/migration/project-root/ppc-manual/vmx/vslh.md

vslh — Vector Shift Left Integer Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000144

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vslh	vslh	—	Vector Shift Left Integer Half Word

Syntax

vslh [VD], [VA], [VB]

Encoding

vslh — form VX

• Opcode word: 0x10000144
• Primary opcode (bits 0–5): 4
• Extended opcode: 324
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vslh: read	Source A vector register.
VB	vslh: read	Source B vector register.
VD	vslh: write	Destination vector register.

Register Effects

vslh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vslh

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vslh"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1419
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:122
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:461
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3884-3891

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vslh => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = a[i] << (b[i] & 0xF); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-lane logical shift-left of half-words. VD.h[i] = VA.h[i] << (VB.h[i] & 0xF) for i ∈ 0..7. Low 4 bits of each shift-count half-word are honoured.
• Per-lane shift counts. Splat with vsplth / vspltish for uniform shifts.
• Zero-fill on the right. Bits lost off the top. No sign propagation — use vsrah if you need arithmetic right shift.
• Big-endian half-word indexing.
• No flags, no VSCR.
• No VMX128 sibling.

Related Instructions

• vsrh — logical-right half-word.
• vsrah — arithmetic-right half-word.
• vrlh — half-word rotate.
• vslb, vslw — byte / word logical-left shifts.
• vsplth, vspltish — splats for shift counts.

IBM Reference

• AIX 7.3 — vslh (Vector Shift Left Integer Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate