e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
173 lines
6.8 KiB
Markdown
173 lines
6.8 KiB
Markdown
# `vspltisw` — Vector Splat Immediate Signed Word
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000038c`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vspltisw` | `vspltisw` | — | Vector Splat Immediate Signed Word |
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| `vspltisw128` | `vspltisw128` | — | Vector128 Splat Immediate Signed Word |
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## Syntax
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```asm
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vspltisw [VD], [SIMM]
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vspltisw128 [VD], [SIMM]
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```
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## Encoding
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### `vspltisw` — form `VX`
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- **Opcode word:** `0x1000038c`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `908`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vspltisw128` — form `VX128_3`
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- **Opcode word:** `0x18000770`
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- **Primary opcode (bits 0–5):** `6`
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- **Extended opcode:** `1904`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (6) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `IMM` | 5-bit immediate |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `SIMM` | vspltisw: read; vspltisw128: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
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| `VD` | vspltisw: write; vspltisw128: write | Destination vector register. |
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## Register Effects
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### `vspltisw`
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- **Reads (always):** `SIMM`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vspltisw128`
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- **Reads (always):** `SIMM`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vspltisw`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vspltisw"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1580`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1580)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:123`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L123)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:516`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L516)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2356-2363`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2356-L2363)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vspltisw | PpcOpcode::vspltisw128 => {
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let simm = ((instr.raw >> 16) & 0x1F) as i32;
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let simm = if simm & 0x10 != 0 { simm | !0x1F } else { simm }; // sign extend 5-bit
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let val = simm as u32;
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let vd = if matches!(instr.opcode, PpcOpcode::vspltisw128) { instr.vd128() } else { instr.rd() };
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ctx.vr[vd] = xenia_types::Vec128::from_u32x4(val, val, val, val);
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ctx.pc += 4;
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}
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```
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</details>
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**`vspltisw128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vspltisw128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1583`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1583)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:123`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L123)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:669`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L669)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2356-2363`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2356-L2363)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vspltisw | PpcOpcode::vspltisw128 => {
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let simm = ((instr.raw >> 16) & 0x1F) as i32;
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let simm = if simm & 0x10 != 0 { simm | !0x1F } else { simm }; // sign extend 5-bit
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let val = simm as u32;
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let vd = if matches!(instr.opcode, PpcOpcode::vspltisw128) { instr.vd128() } else { instr.rd() };
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ctx.vr[vd] = xenia_types::Vec128::from_u32x4(val, val, val, val);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Splat a 5-bit signed immediate across all 4 word lanes.** `SIMM` is sign-extended from 5 bits to 32, so the representable range is `[−16, +15]`.
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- **Constant-generation primitive.** `vspltisw vD, 0` zeroes every lane; `vspltisw vD, -1` generates `{0xFFFFFFFF, …}` (the all-ones vector); `vspltisw vD, 1` is `{1, 1, 1, 1}` — useful for "lane index = 0, 1, 2, 3" constructions via an `lvewx`-style preload followed by this.
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- **No source register.**
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- **No flags, no VSCR.**
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- **VMX128 sibling [`vspltisw128`](vspltisw128.md).**
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## Related Instructions
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- [`vspltisb`](vspltisb.md), [`vspltish`](vspltish.md) — byte / half-word immediate splats.
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- [`vspltw`](vspltw.md) — register-indexed word splat.
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- [`vxor`](vxor.md) — alternative zero-vector idiom.
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## IBM Reference
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- [AIX 7.3 — `vspltisw` (Vector Splat Immediate Signed Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vspltisw-vector-splat-immediate-signed-word-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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