e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
181 lines
6.9 KiB
Markdown
181 lines
6.9 KiB
Markdown
# `vxor` — Vector Logical XOR
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x100004c4`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vxor` | `vxor` | — | Vector Logical XOR |
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| `vxor128` | `vxor128` | — | Vector128 Logical XOR |
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## Syntax
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```asm
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vxor [VD], [VA], [VB]
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vxor128 [VD], [VA], [VB]
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```
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## Encoding
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### `vxor` — form `VX`
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- **Opcode word:** `0x100004c4`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `1220`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vxor128` — form `VX128`
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- **Opcode word:** `0x14000310`
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- **Primary opcode (bits 0–5):** `5`
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- **Extended opcode:** `784`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vxor: read; vxor128: read | Source A vector register. |
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| `VB` | vxor: read; vxor128: read | Source B vector register. |
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| `VD` | vxor: write; vxor128: write | Destination vector register. |
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## Register Effects
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### `vxor`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vxor128`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vxor`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vxor"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:2246`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L2246)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:130`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L130)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:532`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L532)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2235-2243`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2235-L2243)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vxor | PpcOpcode::vxor128 => {
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let (va, vb, vd) = vmx_reg_triple(instr);
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let a = ctx.vr[va].as_u32x4();
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let b = ctx.vr[vb].as_u32x4();
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let mut r = [0u32; 4];
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for i in 0..4 { r[i] = a[i] ^ b[i]; }
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ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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**`vxor128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vxor128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:2249`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L2249)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:130`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L130)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:627`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L627)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2235-2243`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2235-L2243)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vxor | PpcOpcode::vxor128 => {
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let (va, vb, vd) = vmx_reg_triple(instr);
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let a = ctx.vr[va].as_u32x4();
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let b = ctx.vr[vb].as_u32x4();
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let mut r = [0u32; 4];
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for i in 0..4 { r[i] = a[i] ^ b[i]; }
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ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Bitwise XOR across the full 128-bit register.** Lane-agnostic.
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- **`vxor VD, VD, VD` is the canonical "vector zero" idiom.** Every Xenon compiler uses this to materialise the all-zero vector; xenia-rs's interpreter does not special-case it (it still reads the register), but the JIT / translator can fold it at emit time.
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- **Aliasing legal.** `vxor v3, v3, v4` toggles bits from `v4` into `v3`.
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- **No flags, no VSCR.**
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- **VMX128 sibling [`vxor128`](vxor128.md).** Identical semantics; wider register file.
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- **Compare-then-XOR** is the cheapest "mask flip" when `vnor` is not wanted (e.g. to toggle only certain bits, not every bit).
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## Related Instructions
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- [`vor`](vor.md), [`vand`](vand.md), [`vandc`](vandc.md), [`vnor`](vnor.md) — the rest of the Altivec boolean primitives.
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- [`vsel`](vsel.md) — three-input bit-select; equivalent to `(VA & ~VC) | (VB & VC)`.
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- [`vcmpequb`](vcmpequb.md), [`vcmpequh`](vcmpequh.md), [`vcmpequw`](vcmpequw.md) — produce masks XORed against.
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## IBM Reference
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- [AIX 7.3 — `vxor` (Vector Logical XOR)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vxor-vector-logical-xor-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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