xenia-rs/migration/project-root/ppc-manual/vmx128/vcuxwfp128.md

vcuxwfp128 — Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point

Category: VMX128 · Form: VX128_3 · Opcode: 0x180002f0

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcuxwfp128	vcuxwfp128	—	Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point

Syntax

vcuxwfp128 [VD], [VB], [UIMM]

Encoding

vcuxwfp128 — form VX128_3

• Opcode word: 0x180002f0
• Primary opcode (bits 0–5): 6
• Extended opcode: 752
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vcuxwfp128: read	Source B vector register.
UIMM	vcuxwfp128: read	16-bit unsigned immediate. Zero-extended.
VD	vcuxwfp128: write	Destination vector register.

Register Effects

vcuxwfp128

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcuxwfp128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vcuxwfp128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:521
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:98
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:659
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4355-4362

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vcuxwfp128 => {
            let uimm = (instr.raw >> 16) & 0x1F;
            let b = ctx.vr[instr.vb128()].as_u32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = crate::vmx::cvt_u32_to_f32(b[i], uimm); }
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Unsigned fixed-point (uint32) → float with explicit scale. Each lane computes VD[i] = (float)VB.w[i] * 2^-UIMM. Treats the 32-bit input as unsigned, so values ≥ 0x80000000 produce positive floats (unlike vcsxwfp128 which would produce negatives).
• IEEE-754 binary32 output, round-to-nearest. Precision loss above 2^24.
• No VSCR[SAT] effect.
• VSCR[NJ] does not affect the uint → float path.
• VMX128 register-fusion applies.
• No IBM AIX entry — Xenon-only. Closest standard is vcfux.
• No Rc, no XER / FPSCR.

Related Instructions

• vcfux — the standard Altivec uint32 → float with scale.
• vcsxwfp128 — signed-int variant.
• vcfpuxws128, vcfpsxws128 — the inverse (float → int with scale).

IBM Reference

• No IBM AIX entry — Xbox 360 VMX128 extension only.
• Xbox 360 XDK, Altivec-128 (VMX128) extensions; cross-referenced with IBM AltiVec Technology Programmer's Interface Manual §vcfux.