xenia-rs/migration/project-root/ppc-manual/vmx128/vcfpsxws128.md

vcfpsxws128 — Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate

Category: VMX128 · Form: VX128_3 · Opcode: 0x18000230

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcfpsxws128	vcfpsxws128	—	Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate

Syntax

vcfpsxws128 [VD], [VB], [UIMM]

Encoding

vcfpsxws128 — form VX128_3

• Opcode word: 0x18000230
• Primary opcode (bits 0–5): 6
• Extended opcode: 560
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vcfpsxws128: read	Source B vector register.
UIMM	vcfpsxws128: read	16-bit unsigned immediate. Zero-extended.
VD	vcfpsxws128: write	Destination vector register.
VSCR	vcfpsxws128: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vcfpsxws128

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vcfpsxws128: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcfpsxws128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vcfpsxws128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:539
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:93
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:656
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4323-4334

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vcfpsxws128 => {
            let uimm = (instr.raw >> 16) & 0x1F;
            let b = ctx.vr[instr.vb128()].as_f32x4();
            let mut r = [0i32; 4]; let mut sat = false;
            for i in 0..4 {
                let (v, s) = crate::vmx::cvt_f32_to_i32_sat(b[i], uimm);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.vd128()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Float → signed fixed-point (int32) with explicit scale. Each lane computes VD.w[i] = sat_int32(VB[i] * 2^UIMM), truncating toward zero and clamping to [−2^31, 2^31−1]. UIMM is a 5-bit unsigned bias (range 0..31) that specifies a power-of-two pre-scale on the float value.
• Use case: fixed-point pipelines. The UIMM pre-scale lets game code convert a [0.0, 1.0] float channel into a uint16-range fixed-point value in one instruction (e.g. UIMM = 15 → scale by 32768).
• Sticky VSCR[SAT] set whenever a lane clamps (including NaN inputs, which xenia's cvt_f32_to_i32_sat treats as 0 and flags saturation).
• VSCR[NJ] honoured on the float input side.
• VMX128 register-fusion applies to VD and VB: 7-bit register IDs via VD128l ‖ VD128h and VB128l ‖ VB128h.
• No IBM AIX entry — this is Xenon-only. The closest standard Altivec op is vctsxs.
• No Rc, no XER / FPSCR.

Related Instructions

• vctsxs — the standard Altivec equivalent (same semantics, 32-register file).
• vcfpuxws128 — unsigned variant (clamps to uint32).
• vcsxwfp128, vcuxwfp128 — the inverse (int → float with scale).
• vrfiz — plain truncate-to-float-integer without scale.

IBM Reference

• No IBM AIX entry — this instruction is exclusive to the Xbox 360's VMX128 extension.
• Xbox 360 XDK, Altivec-128 (VMX128) extensions (Microsoft internal documentation); semantics cross-referenced with IBM AltiVec Technology Programmer's Interface Manual §vctsxs.