Sylpheed/tools/ppc-manual/alu/oris.md

oris — OR Immediate Shifted

Category: Integer ALU · Form: D · Opcode: 0x64000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
oris	oris	—	OR Immediate Shifted

Syntax

oris [RA], [RS], [UIMM]

Encoding

oris — form D

• Opcode word: 0x64000000
• Primary opcode (bits 0–5): 25
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	oris: read	Source GPR (alias for RD in some stores).
UIMM	oris: read	16-bit unsigned immediate. Zero-extended.
RA	oris: write	Source GPR (r0–r31).

Register Effects

oris

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

RA <- (RS) | (UIMM || 0x0000)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

oris

• Canary XML: tools/ppc-instructions.xml — search for mnem="oris"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:821
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:201
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:463

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_oris(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) | (i32.0 || UI || i16.0)
  Value* ra =
      f.Or(f.LoadGPR(i.D.RT), f.LoadConstantUint64(XEEXTZ16(i.D.DS) << 16));
  f.StoreGPR(i.D.RA, ra);
  return 0;
}

Special Cases & Edge Conditions

• No record form. No oris. — same as ori. For CR0 updates use orx with Rc=1.
• Immediate is zero-extended then shifted left 16. Only bits 32–47 of RA (in PowerISA bit numbering) can be affected; the high 32 bits and low 16 bits of RA come from RS unchanged.
• Common pair with lis to load a 32-bit constant: lis r3, hi16 (= addis r3, 0, hi16), then ori r3, r3, lo16. For unsigned constants whose low half has the high bit set, lis followed by ori works cleanly because ori is zero-extending; using addi instead would sign-extend lo16 and corrupt the constant.
• 64-bit operation in Canary. f.Or(RS, EXTZ16(UI) << 16) on the full u64.
• No XER, no CR effect. Pure register OR.
• RA = 0 reads r0 (not literal zero); see ori.

Related Instructions

• ori — companion (immediate not shifted).
• addis — D-form add-immediate-shifted; pairs with ori to build constants.
• xoris, andisx — sister immediate-shifted logicals.

IBM Reference

• AIX 7.3 — oris (OR Immediate Shifted)