Sylpheed/tools/ppc-manual/alu/ori.md

ori — OR Immediate

Category: Integer ALU · Form: D · Opcode: 0x60000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
ori	ori	—	OR Immediate

Syntax

ori [RA], [RS], [UIMM]

Encoding

ori — form D

• Opcode word: 0x60000000
• Primary opcode (bits 0–5): 24
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	ori: read	Source GPR (alias for RD in some stores).
UIMM	ori: read	16-bit unsigned immediate. Zero-extended.
RA	ori: write	Source GPR (r0–r31).

Register Effects

ori

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

RA <- (RS) | (0x0000 || UIMM)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

ori

• Canary XML: tools/ppc-instructions.xml — search for mnem="ori"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:810
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:200
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:462

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_ori(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) | (i48.0 || UI)
  if (!i.D.RA && !i.D.RT && !i.D.DS) {
    f.Nop();
    return 0;
  }
  Value* ra = f.Or(f.LoadGPR(i.D.RT), f.LoadConstantUint64(XEEXTZ16(i.D.DS)));
  f.StoreGPR(i.D.RA, ra);
  return 0;
}

Special Cases & Edge Conditions

• No record form. Unlike andix, ori does not update CR0 — there is no ori.. If you need a CR update after OR-immediate, follow it with cmpwi or use orx with Rc=1.
• Immediate is zero-extended. Only the low 16 bits of RA can be affected; the high 48 bits are passed through from RS unchanged.
• ori 0, 0, 0 is the canonical NOP. All PowerPC NOPs assemble to this encoding (0x60000000). Disassemblers usually display this as nop.
• Common idiom: build a 32-bit constant via lis + ori. lis r3, hi16; ori r3, r3, lo16 materialises any 32-bit immediate with no CR or XER disturbance.
• 64-bit operation in Canary. f.Or(RS, EXTZ16(UI)) on the full u64; the high bits come from RS unchanged. The canonical no-op ori 0, 0, 0 is special-cased to f.Nop().
• RA = 0 reads r0 (not the literal zero). Different from addi's RA0 semantics; ori uses the regular RA interpretation.

Related Instructions

• oris — same op with the immediate shifted left 16.
• orx — register-register; supports Rc=1.
• xori, xoris, andix, andisx — sister immediate logicals.
• nop (simplified) — ori 0, 0, 0.

IBM Reference

• AIX 7.3 — ori (OR Immediate)
• AIX 7.3 — nop (simplified)