Sylpheed/tools/ppc-manual/fpu/fmrx.md

fmrx — Floating Move Register

Category: Floating-Point · Form: X · Opcode: 0xfc000090

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fmr	fmrx	—	Floating Move Register
fmr.	fmrx	Rc=1	Floating Move Register

Syntax

fmr[Rc] [FD], [FB]

Encoding

fmrx — form X

• Opcode word: 0xfc000090
• Primary opcode (bits 0–5): 63
• Extended opcode: 72
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fmrx: read	Source B floating-point register.
FD	fmrx: write	Destination floating-point register.
CR	fmrx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

fmrx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• fmrx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

FRT <- FRB

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fmrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fmrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:496
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:78
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1021

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fmrx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- (frB)
  Value* v = f.LoadFPR(i.X.RB);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  return 0;
}

Special Cases & Edge Conditions

• Bit-pattern copy, no rounding. fmr copies the 64-bit binary representation of FRB into FRT unchanged. No precision loss, no FPSCR exception bits, no NaN quietening. Canary copies the value bit-exactly, but also runs its UpdateFPSCR stub, which clears FPSCR[FEX, VX] — bits a real fmr leaves alone.
• NaN preserved verbatim. Signalling/quiet bit, payload, and sign are all preserved exactly. Unlike arithmetic instructions, fmr does not quieten signalling NaNs.
• Special values. All bit patterns pass through untouched, including ±0, ±∞, and any NaN. The destination receives an exact copy.
• FPSCR. Hardware does not update FPRF or any exception bit. The "FPSCR write" implied in the header refers only to Rc=1 updating CR1 from existing FPSCR contents.
• Rc=1 (fmr.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• No FRA. X-form, primary 63, XO 72. Reads FRB only.
• Cheaper than load-store. Compilers emit fmr for FPR-to-FPR moves; transferring a value via memory (stfd/lfd) would be far more expensive.

Related Instructions

• fabsx, fnegx, fnabsx — sign-bit variants of the move (clear / toggle / set).
• fselx — branch-free select; like a conditional fmr.
• mffsx — read FPSCR into an FPR; complementary "FPR move" for a control register.
• stfd/lfd — memory-mediated FPR transfer (much slower; used for register window spills).

IBM Reference

• AIX 7.3 — fmr (Floating Move Register)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (move-class instructions explicitly bypass quietening and FPSCR side effects).