Sylpheed/tools/ppc-manual/fpu/fnegx.md

fnegx — Floating Negate

Category: Floating-Point · Form: X · Opcode: 0xfc000050

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fneg	fnegx	—	Floating Negate
fneg.	fnegx	Rc=1	Floating Negate

Syntax

fneg[Rc] [FD], [FB]

Encoding

fnegx — form X

• Opcode word: 0xfc000050
• Primary opcode (bits 0–5): 63
• Extended opcode: 40
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fnegx: read	Source B floating-point register.
FD	fnegx: write	Destination floating-point register.
CR	fnegx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

fnegx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• fnegx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

FRT <- flip_sign(FRB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fnegx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fnegx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:515
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:84
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1018

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fnegx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- ¬ frB[0] || frB[1-63]
  Value* v = f.Neg(f.LoadFPR(i.X.RB));
  f.StoreFPR(i.X.RT, v);
  // f.UpdateFPSCR(v, i.X.Rc);
  if (i.X.Rc) {
    // todo
  }
  return 0;
}

Special Cases & Edge Conditions

• Bit-pattern operation, no rounding. fneg toggles the sign bit (bit 0) of the source binary64 value and writes the 64-bit pattern to the destination. No precision change, no exception bits.
• NaN handling. PowerISA specifies that fneg toggles the NaN sign bit (unlike fnmadd which does not). Canary's Neg is vxorpd with the sign mask, which toggles NaN signs too — a match. ⚠️ Its Rc=1 branch is empty, so fneg. does not update CR1 in Canary.
• Special values. fneg(+0) = -0; fneg(-0) = +0; fneg(±∞) = ∓∞. No FPSCR[VXSNAN] raised even on signalling NaN inputs (sign-bit ops are not arithmetic).
• FPSCR. Hardware does not update FPRF and does not raise any exception bit. The "FPSCR write" in the header refers only to Rc=1 updating CR1 from existing FPSCR contents.
• Rc=1 (fneg.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• No FRA. X-form, primary 63, XO 40. Reads FRB only.
• Use as a free negate. Common in compiled PPC code for -x or as part of negate-and-fma sequences when no fused negative variant exists.

Related Instructions

• fabsx — clear sign bit (positive).
• fnabsx — set sign bit (negative).
• fmrx — plain register copy.
• fnmaddx, fnmsubx, fnmaddsx, fnmsubsx — fused negate-multiply-add forms; eliminate the need for an explicit fneg after an FMA.
• fselx — combined with fneg for branch-free copysign/clamp patterns.

IBM Reference

• AIX 7.3 — fneg (Floating Negate)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (PPC's fneg toggles NaN sign — distinct from the fnmadd family).