Sylpheed/tools/ppc-manual/fpu/fselx.md

fselx — Floating Select

Category: Floating-Point · Form: A · Opcode: 0xfc00002e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fsel	fselx	—	Floating Select
fsel.	fselx	Rc=1	Floating Select

Syntax

fsel[Rc] [FD], [FA], [FC], [FB]

Encoding

fselx — form A

• Opcode word: 0xfc00002e
• Primary opcode (bits 0–5): 63
• Extended opcode: 23
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fselx: read	Source A floating-point register (fr0–fr31).
FC	fselx: read	Source C floating-point register (for madd-style ops).
FB	fselx: read	Source B floating-point register.
FD	fselx: write	Destination floating-point register.
CR	fselx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

fselx

• Reads (always): FA, FC, FB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• fselx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fselx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fselx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:144
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:92
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1039

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fselx(PPCHIRBuilder& f, const InstrData& i) {
  // if (frA) >= 0.0
  // then frD <- (frC)
  // else frD <- (frB)
  Value* ge = f.CompareSGE(f.LoadFPR(i.A.FRA), f.LoadZeroFloat64());
  Value* v = f.Select(ge, f.LoadFPR(i.A.FRC), f.LoadFPR(i.A.FRB));
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}

Special Cases & Edge Conditions

• Non-IEEE branch-free select. PowerPC-specific; not in the IEEE-754 spec. Semantics: FRT = (FRA >= 0.0) ? FRC : FRB. Used pervasively in compiled PPC for min/max/clamp/copysign without branches. Canary emits Select(CompareSGE(FRA, 0.0), FRC, FRB); the x64 compare is vcomisd + setae, which is false for a NaN, so a NaN in FRA selects FRB as on PPC.
• -0.0 selects FRC. Per PowerISA, -0 compares as >= 0, so it routes to FRC (the "true" branch). Canary's vcomisd reports -0.0 equal to 0.0, so setae is true — a match.
• NaN selects FRB. Per PowerISA, NaN does not satisfy >= 0, so the result is FRB. Canary's vcomisd + setae is false for an unordered compare, so FRB is selected. Match.
• No FPSCR side effects. fsel does not raise VXSNAN even on signalling NaN inputs, and does not update FPRF. It is purely a data-movement op.
• Rc=1 (fsel.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• A-form encoding. Reads FRA, FRB, FRC, writes FRT. Assembler order: fsel FD, FA, FC, FB (note: FRC before FRB).
• Common idioms.
  • min(a,b) = fsel(a-b, b, a)
  • max(a,b) = fsel(a-b, a, b)
  • clamp(x, lo, hi) = fsel(x-lo, fsel(hi-x, x, hi), lo)
  • copysign(x, y) = fsel(y, |x|, -|x|) (using fabs/fnabs)
• Optional ISA. fsel is an optional PowerISA instruction; some implementations trap. Xenon implements it natively.
• No precision change. Bit-pattern selection — no rounding regardless of source precision.

Related Instructions

• fabsx, fnegx, fnabsx — sign-bit ops; common companions for fsel-based copysign/clamp idioms.
• fsubx — subtract is the standard way to produce the comparison key (a - b).
• fcmpux, fcmpox — IEEE compare with branch; the heavyweight alternative to fsel.
• fmrx — unconditional copy.

IBM Reference

• AIX 7.3 — fsel (Floating Select)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (note: fsel is non-IEEE and uses the >= 0 convention, not > 0).