Sylpheed/tools/ppc-manual/vmx/vaddsws.md

vaddsws — Vector Add Signed Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000380

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vaddsws	vaddsws	—	Vector Add Signed Word Saturate

Syntax

vaddsws [VD], [VA], [VB]

Encoding

vaddsws — form VX

• Opcode word: 0x10000380
• Primary opcode (bits 0–5): 4
• Extended opcode: 896
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vaddsws: read	Source A vector register.
VB	vaddsws: read	Source B vector register.
VD	vaddsws: write	Destination vector register.
VSCR	vaddsws: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vaddsws

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vaddsws: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vaddsws

• Canary XML: tools/ppc-instructions.xml — search for mnem="vaddsws"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:364
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:300
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:627

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vaddsws(PPCHIRBuilder& f, const InstrData& i) {
  Value* v = f.VectorAdd(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT32_TYPE,
                         ARITHMETIC_SATURATE);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Four signed-word lanes, saturating. Each VD[i] = clamp(VA[i] + VB[i], INT32_MIN, INT32_MAX) for i = 0..3. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• VSCR[SAT] is sticky-set if any lane clamps. ⚠️ Canary never records SAT: its StoreSAT(DidSaturate(v)) writes a private vscr_sat byte, the x64 DID_SATURATE is a stub that always yields 0, and mfvscr reads vscr_vec, which only mtvscr changes.
• No multi-precision carry. Unlike vaddcuw, vaddsws does not expose a per-lane carry/borrow — a saturated lane simply clips; it does not overflow into the adjacent lane.
• Asymmetric clamp. INT32_MAX + 1 = INT32_MAX; INT32_MIN + (-1) = INT32_MIN.
• The modulo sibling is vadduwm. Modulo add for signed and unsigned words is bit-identical; switch to vaddsws only when clipping with sign awareness is desired.
• No XER side effects.
• No VMX128 sibling.
• Common usage. Accumulate four 32-bit signed sums per cycle (e.g. dot products of int16 lanes after a vmsumshs — which already saturates internally — for further accumulation across multiple iterations).

Related Instructions

• vadduws — same width, unsigned saturating add.
• vadduwm — same width, modulo (non-saturating) add; sign-agnostic.
• vaddsbs, vaddshs — signed saturating add at byte / half width.
• vsubsws — the matching signed saturating subtract.
• vmsumshs, vmsumuhs — saturating multiply-sum that often feeds a vaddsws chain.
• mtvscr / mfvscr — read or clear the VSCR[SAT] bit.

IBM Reference

• AIX 7.3 — vaddsws (Vector Add Signed Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic