f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
182 lines
7.3 KiB
Markdown
182 lines
7.3 KiB
Markdown
# `vandc` — Vector Logical AND with Complement
|
||
|
||
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000444`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `vandc` | `vandc` | — | Vector Logical AND with Complement |
|
||
| `vandc128` | `vandc128` | — | Vector128 Logical AND with Complement |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
vandc [VD], [VA], [VB]
|
||
vandc128 [VD], [VA], [VB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `vandc` — form `VX`
|
||
|
||
- **Opcode word:** `0x10000444`
|
||
- **Primary opcode (bits 0–5):** `4`
|
||
- **Extended opcode:** `1092`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4) |
|
||
| 6–10 | `VRT/VD` | destination vector register |
|
||
| 11–15 | `VRA/VA` | source A vector register |
|
||
| 16–20 | `VRB/VB` | source B vector register |
|
||
| 21–31 | `XO` | extended opcode (11 bits) |
|
||
|
||
### `vandc128` — form `VX128`
|
||
|
||
- **Opcode word:** `0x14000250`
|
||
- **Primary opcode (bits 0–5):** `5`
|
||
- **Extended opcode:** `592`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4 or 5) |
|
||
| 6–10 | `VD128l` | destination low 5 bits |
|
||
| 11–15 | `VA128l` | source A low 5 bits |
|
||
| 16–20 | `VB128l` | source B low 5 bits |
|
||
| 21 | `VA128H` | source A high bit |
|
||
| 22 | `—` | reserved |
|
||
| 23–25 | `VC` | optional VC / XO sub-field |
|
||
| 26 | `VA128h` | source A middle bit |
|
||
| 27 | `—` | reserved |
|
||
| 28–29 | `VD128h` | destination high 2 bits |
|
||
| 30–31 | `VB128h` | source B high 2 bits |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `VA` | vandc: read; vandc128: read | Source A vector register. |
|
||
| `VB` | vandc: read; vandc128: read | Source B vector register. |
|
||
| `VD` | vandc: write; vandc128: write | Destination vector register. |
|
||
|
||
## Register Effects
|
||
|
||
### `vandc`
|
||
|
||
- **Reads (always):** `VA`, `VB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
### `vandc128`
|
||
|
||
- **Reads (always):** `VA`, `VB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
; No hand-written pseudocode for this instruction yet.
|
||
; The authoritative semantics are the Canary emitter snapshot under
|
||
; Implementation References; about half of Canary's emitters open
|
||
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
|
||
; Every side effect is also enumerated in the Register Effects and
|
||
; Status-Register Effects tables above.
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* No hand-written C yet. Translate the Canary emitter snapshot */
|
||
/* under Implementation References; its HIR maps directly: */
|
||
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
|
||
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
|
||
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
|
||
/* wrap them in f.ByteSwap for the big-endian guest value */
|
||
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
|
||
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
|
||
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`vandc`**
|
||
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vandc"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
|
||
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:436`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L436)
|
||
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:309`](../../../crates/sylpheed-ppc/src/opcode.rs#L309)
|
||
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:641`](../../../crates/sylpheed-ppc/src/decoder.rs#L641)
|
||
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
|
||
|
||
```cpp
|
||
int InstrEmit_vandc(PPCHIRBuilder& f, const InstrData& i) {
|
||
return InstrEmit_vandc_(f, i.VX.VD, i.VX.VA, i.VX.VB);
|
||
}
|
||
|
||
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:430) ──
|
||
int InstrEmit_vandc_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
|
||
// VD <- (VA) & ¬(VB)
|
||
Value* v = f.AndNot(f.LoadVR(va), f.LoadVR(vb));
|
||
f.StoreVR(vd, v);
|
||
return 0;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
**`vandc128`**
|
||
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vandc128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
|
||
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:439`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L439)
|
||
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:310`](../../../crates/sylpheed-ppc/src/opcode.rs#L310)
|
||
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:736`](../../../crates/sylpheed-ppc/src/decoder.rs#L736)
|
||
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
|
||
|
||
```cpp
|
||
int InstrEmit_vandc128(PPCHIRBuilder& f, const InstrData& i) {
|
||
return InstrEmit_vandc_(f, VX128_VD128, VX128_VA128, VX128_VB128);
|
||
}
|
||
|
||
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:430) ──
|
||
int InstrEmit_vandc_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
|
||
// VD <- (VA) & ¬(VB)
|
||
Value* v = f.AndNot(f.LoadVR(va), f.LoadVR(vb));
|
||
f.StoreVR(vd, v);
|
||
return 0;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **Bitwise AND-with-complement of the full 128 bits.** `VD = VA & ~VB`. Lane width is irrelevant — the operation is bit-for-bit. Order matters: `vandc VA, VB` is *not* the same as `vandc VB, VA`.
|
||
- **Standard "clear bits in mask" idiom.** Drop bits selected by the mask in `VB`: `vandc VD, VD, vMask`. Equivalent to `VD &= ~vMask`. Cheaper than synthesising the complement first with [`vnor`](vnor.md) and then ANDing.
|
||
- **Compare → mask → mask-out idiom.** A compare produces per-lane all-ones; pair with `vandc` to keep only the lanes where the compare was *false*. The complement avoids an extra [`vnor`](vnor.md) or `vxor` with all-ones.
|
||
- **No flags, no exceptions, no `VSCR` interaction.**
|
||
- **Aliasing legal.** `vandc VD, VD, VD` clears `VD` (`x & ~x = 0`).
|
||
- **VMX128 sibling (`vandc128`).** Identical semantics with the extended 128-register encoding; Canary's `vandc128` shares `vandc`'s body after decoding the 7-bit indices.
|
||
|
||
## Related Instructions
|
||
|
||
- [`vand`](vand.md) — the un-complemented sibling.
|
||
- [`vor`](vor.md), [`vxor`](vxor.md), [`vnor`](vnor.md) — the rest of the bitwise family.
|
||
- [`vsel`](vsel.md) — bitwise select using a third register; useful when the "false" branch is non-zero.
|
||
- [`vcmpequb`](vcmpequb.md) and other compares — natural mask producers.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `vandc` (Vector Logical AND with Complement)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vandc-vector-logical-complement-instruction)
|
||
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Logical Operations](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
|