Sylpheed/tools/ppc-manual/vmx/vcmpgtsh.md

vcmpgtsh — Vector Compare Greater-Than Signed Half Word

Category: VMX (Altivec) · Form: VC · Opcode: 0x10000346

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcmpgtsh	vcmpgtsh	—	Vector Compare Greater-Than Signed Half Word
vcmpgtsh.	vcmpgtsh	Rc=1	Vector Compare Greater-Than Signed Half Word

Syntax

vcmpgtsh[Rc] [VD], [VA], [VB]

Encoding

vcmpgtsh — form VC

• Opcode word: 0x10000346
• Primary opcode (bits 0–5): 4
• Extended opcode: 838
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21	Rc	record-form flag (updates CR6)
22–31	XO	extended opcode (10 bits)

Operands

Field	Role	Description
VA	vcmpgtsh: read	Source A vector register.
VB	vcmpgtsh: read	Source B vector register.
VD	vcmpgtsh: write	Destination vector register.
CR	vcmpgtsh: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

vcmpgtsh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

Status-Register Effects

• vcmpgtsh: CR6 ← [all-true, 0, all-false, 0] when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcmpgtsh

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcmpgtsh"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:739
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:334
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:682

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcmpgtsh(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpxxi_(f, i, vcmpxxi_gt_signed, 2, i.VXR.VD, i.VXR.VA,
                            i.VXR.VB, i.VXR.Rc);
}

Special Cases & Edge Conditions

• Per-half mask: all-ones / all-zero. Eight half-word lanes; VD[i] = (int16(VA[i]) > int16(VB[i])) ? 0xFFFF : 0x0000. Lane 0 is the most-significant half.
• Sign matters. 0x8000 > 0x0001 is true unsigned but false signed (-32768 > 1). Pick vcmpgtsh deliberately when sign bit affects ordering.
• CR6 update when Rc=1 (vcmpgtsh.). CR6 = [lt = all-true, gt = 0, eq = all-false, so = 0].
• Compose with vsel. Mask drives vsel per half.
• Common usage. Q15 audio threshold detection, signed image-processing kernels.
• No VSCR interaction, no XER, no traps.
• Aliasing legal.
• No VMX128 sibling.

Related Instructions

• vcmpgtuh — same width, unsigned >.
• vcmpequh — equality at half width.
• vcmpgtsb, vcmpgtsw — signed > at byte / word width.
• vsel, vand, vandc, vor, vxor — mask consumers / combinators.
• vmaxsh, vminsh — direct signed max / min.

IBM Reference

• AIX 7.3 — vcmpgtsh (Vector Compare Greater-Than Signed Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares