Sylpheed/tools/ppc-manual/vmx/vxor.md

vxor — Vector Logical XOR

Category: VMX (Altivec) · Form: VX · Opcode: 0x100004c4

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vxor	vxor	—	Vector Logical XOR
vxor128	vxor128	—	Vector128 Logical XOR

Syntax

vxor [VD], [VA], [VB]
vxor128 [VD], [VA], [VB]

Encoding

vxor — form VX

• Opcode word: 0x100004c4
• Primary opcode (bits 0–5): 4
• Extended opcode: 1220
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vxor128 — form VX128

• Opcode word: 0x14000310
• Primary opcode (bits 0–5): 5
• Extended opcode: 784
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vxor: read; vxor128: read	Source A vector register.
VB	vxor: read; vxor128: read	Source B vector register.
VD	vxor: write; vxor128: write	Destination vector register.

Register Effects

vxor

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vxor128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vxor

• Canary XML: tools/ppc-instructions.xml — search for mnem="vxor"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2232
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:494
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:647

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vxor(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vxor_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:2220) ──
int InstrEmit_vxor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) ^ (VB)
  Value* v;
  if (va == vb) {
    // Fast clear.
    v = f.LoadZeroVec128();
  } else {
    v = f.Xor(f.LoadVR(va), f.LoadVR(vb));
  }
  f.StoreVR(vd, v);
  return 0;
}

vxor128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vxor128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2235
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:495
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:742

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vxor128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vxor_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:2220) ──
int InstrEmit_vxor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) ^ (VB)
  Value* v;
  if (va == vb) {
    // Fast clear.
    v = f.LoadZeroVec128();
  } else {
    v = f.Xor(f.LoadVR(va), f.LoadVR(vb));
  }
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Bitwise XOR across the full 128-bit register. Lane-agnostic.
• vxor VD, VD, VD is the canonical "vector zero" idiom. Every Xenon compiler uses this to materialise the all-zero vector; Canary special-cases it at translate time — when VA == VB it stores a zero vector without reading the register.
• Aliasing legal. vxor v3, v3, v4 toggles bits from v4 into v3.
• No flags, no VSCR.
• VMX128 sibling vxor128. Identical semantics; wider register file.
• Compare-then-XOR is the cheapest "mask flip" when vnor is not wanted (e.g. to toggle only certain bits, not every bit).

Related Instructions

• vor, vand, vandc, vnor — the rest of the Altivec boolean primitives.
• vsel — three-input bit-select; equivalent to (VA & ~VC) | (VB & VC).
• vcmpequb, vcmpequh, vcmpequw — produce masks XORed against.

IBM Reference

• AIX 7.3 — vxor (Vector Logical XOR)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations