Sylpheed/tools/ppc-manual/vmx/vor.md

vor — Vector Logical OR

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000484

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vor	vor	—	Vector Logical OR
vor128	vor128	—	Vector128 Logical OR

Syntax

vor [VD], [VA], [VB]
vor128 [VD], [VA], [VB]

Encoding

vor — form VX

• Opcode word: 0x10000484
• Primary opcode (bits 0–5): 4
• Extended opcode: 1156
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vor128 — form VX128

• Opcode word: 0x140002d0
• Primary opcode (bits 0–5): 5
• Extended opcode: 720
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vor: read; vor128: read	Source A vector register.
VB	vor: read; vor128: read	Source B vector register.
VD	vor: write; vor128: write	Destination vector register.

Register Effects

vor

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vor128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vor

• Canary XML: tools/ppc-instructions.xml — search for mnem="vor"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1162
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:398
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:646

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vor(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vor_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1151) ──
int InstrEmit_vor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) | (VB)
  if (va == vb) {
    // Copy VA==VB into VD.
    f.StoreVR(vd, f.LoadVR(va));
  } else {
    Value* v = f.Or(f.LoadVR(va), f.LoadVR(vb));
    f.StoreVR(vd, v);
  }
  return 0;
}

vor128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vor128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1165
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:399
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:740

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vor128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vor_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1151) ──
int InstrEmit_vor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) | (VB)
  if (va == vb) {
    // Copy VA==VB into VD.
    f.StoreVR(vd, f.LoadVR(va));
  } else {
    Value* v = f.Or(f.LoadVR(va), f.LoadVR(vb));
    f.StoreVR(vd, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Bitwise OR across the full 128-bit register. Lane-agnostic; Canary emits one 128-bit Or (or a plain copy when VA == VB), identical at any granularity.
• vor VD, VA, VA is the idiomatic register move. No dedicated "vmr" exists in base Altivec; compilers recognise the vor v3, v4, v4 pattern as a move and schedule accordingly.
• Aliasing is legal. vor v3, v3, v4 merges the mask in v4 into v3.
• No flags, no VSCR effect.
• VMX128 sibling vor128. Same operation, wider register file.
• Common pattern: ORing a compare mask with a data vector to force specific lanes to all-ones without needing a select.

Related Instructions

• vand, vandc — AND / AND-with-complement.
• vnor — NOR, includes the idiom for bitwise NOT.
• vxor — XOR; also a common "zero register" via vxor vD, vD, vD.
• vsel — three-operand bit-select, often combined with OR of masks.

IBM Reference

• AIX 7.3 — vor (Vector Logical OR)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations