Sylpheed/tools/ppc-manual/vmx/vnor.md

vnor — Vector Logical NOR

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000504

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vnor	vnor	—	Vector Logical NOR
vnor128	vnor128	—	Vector128 Logical NOR

Syntax

vnor [VD], [VA], [VB]
vnor128 [VD], [VA], [VB]

Encoding

vnor — form VX

• Opcode word: 0x10000504
• Primary opcode (bits 0–5): 4
• Extended opcode: 1284
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vnor128 — form VX128

• Opcode word: 0x14000290
• Primary opcode (bits 0–5): 5
• Extended opcode: 656
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vnor: read; vnor128: read	Source A vector register.
VB	vnor: read; vnor128: read	Source B vector register.
VD	vnor: write; vnor128: write	Destination vector register.

Register Effects

vnor

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vnor128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vnor

• Canary XML: tools/ppc-instructions.xml — search for mnem="vnor"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1144
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:396
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:649

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vnor(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vnor_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1138) ──
int InstrEmit_vnor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- ¬((VA) | (VB))
  Value* v = f.Not(f.Or(f.LoadVR(va), f.LoadVR(vb)));
  f.StoreVR(vd, v);
  return 0;
}

vnor128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vnor128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1147
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:397
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:738

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vnor128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vnor_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1138) ──
int InstrEmit_vnor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- ¬((VA) | (VB))
  Value* v = f.Not(f.Or(f.LoadVR(va), f.LoadVR(vb)));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Bitwise NOR across the full 128-bit register. VD = ~(VA | VB). The operation is lane-agnostic; PPC documents it per-bit, and Canary emits Not(Or(VA, VB)) over the whole vector — identical to any 32-bit, 16-bit or 8-bit decomposition.
• vnor VD, VA, VA is the idiomatic vnot (bitwise complement of VA). No dedicated vnot exists in base Altivec.
• Aliasing is legal. vnor v3, v3, v4 or vnor v3, v3, v3 are well-defined and common.
• No flags. No CR, XER, VSCR side-effect.
• VMX128 sibling vnor128 provides the same op with access to v0..v127; Canary's vnor128 decodes the 7-bit indices and shares vnor's body.
• Useful for mask inversion. When a compare result needs to be inverted — e.g. "where not equal" — vnor of the compare result with itself is cheaper than a dedicated inversion.

Related Instructions

• vand — bitwise AND.
• vandc — VA & ~VB (useful as a fused inversion on the B side).
• vor, vxor — complete the boolean-primitive set.
• vsel — three-input bit-select; often fed by the inverse of a compare mask.
• vcmpequb and related compares — produce the masks vnor is typically applied to.

IBM Reference

• AIX 7.3 — vnor (Vector Logical NOR)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations