Sylpheed/tools/ppc-manual/alu/sldx.md

sldx — Shift Left Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000036

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sld	sldx	—	Shift Left Doubleword
sld.	sldx	Rc=1	Shift Left Doubleword

Syntax

sld[Rc] [RA], [RS], [RB]

Encoding

sldx — form X

• Opcode word: 0x7c000036
• Primary opcode (bits 0–5): 31
• Extended opcode: 27
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sldx: read	Source GPR (alias for RD in some stores).
RB	sldx: read	Source GPR.
RA	sldx: write	Source GPR (r0–r31).
CR	sldx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

sldx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• sldx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[57:63]
RA <- ((RS) << n)                       if n < 64 else 0

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sldx

• Canary XML: tools/ppc-instructions.xml — search for mnem="sldx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1122
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:216
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:874

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sldx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- (RB)[58:63]
  // r <- ROTL64((RS), n)
  // if (RB)[57] = 0 then
  //   m <- MASK(0, 63-n)
  // else
  //   m <- i64.0
  // RA <- r & m
  Value* sh =
      f.And(f.Truncate(f.LoadGPR(i.X.RB), INT8_TYPE), f.LoadConstantInt8(0x7F));
  Value* v = f.Select(f.IsTrue(f.Shr(sh, 6)), f.LoadZeroInt64(),
                      f.Shl(f.LoadGPR(i.X.RT), sh));
  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 64-bit logical left shift. RA ← RS << (RB & 0x7F) if the shift count is < 64, otherwise RA = 0. Bits shifted past bit 0 are discarded.
• Critical: shift count is 7 bits, not 6. PowerISA reads RB[57:63] (7 bits, 0..127). Counts in [64, 127] produce zero, not RS << (count mod 64). Canary respects this: sh = RB & 0x7F, then Select(sh >> 6, 0, RS << sh). C's undefined behaviour for << with a count >= width is a spec-violation source if you translate naïvely.
• No XER[CA] produced by left shifts. Logical right srdx and arithmetic right sradx differ here — arithmetic right does set CA.
• Rc=1 CR0 update is 32-bit in Canary (f.UpdateCR(0, v)); spec compares the full 64-bit shifted value (which is 0 for shifts ≥ 64).
• Strength-reduced from mulli for power-of-two multipliers.
• No OE bit.

Related Instructions

• slwx — 32-bit logical left shift.
• srdx — 64-bit logical right shift.
• sradx, sradix — 64-bit arithmetic right shifts.
• rldicrx — sldi simplified mnemonic uses this.
• mulli — for non-power-of-two multipliers.

IBM Reference

• AIX 7.3 — sld (Shift Left Doubleword)