Sylpheed/tools/ppc-manual/alu/sradx.md

sradx — Shift Right Algebraic Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000634

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srad	sradx	—	Shift Right Algebraic Doubleword
srad.	sradx	Rc=1	Shift Right Algebraic Doubleword

Syntax

srad[Rc] [RA], [RS], [RB]

Encoding

sradx — form X

• Opcode word: 0x7c000634
• Primary opcode (bits 0–5): 31
• Extended opcode: 794
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sradx: read	Source GPR (alias for RD in some stores).
RB	sradx: read	Source GPR.
RA	sradx: write	Source GPR (r0–r31).
CR	sradx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	sradx: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

sradx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• sradx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

n <- (RB)[57:63]
RA <- ((RS) >>a n) sign-extended        if n < 64
CA <- (RS signed < 0) && any_bit_shifted_out

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sradx

• Canary XML: tools/ppc-instructions.xml — search for mnem="sradx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1201
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:219
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:956

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sradx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- rB[58-63]
  // r <- ROTL[64](rS, 64 - n)
  // if rB[57] = 0 then m ← MASK(n, 63)
  // else m ← (64)0
  // S ← rS[0]
  // rA <- (r & m) | (((64)S) & ¬ m)
  // XER[CA] <- S & ((r & ¬ m) ¦ 0)
  // if n == 0: rA <- rS, XER[CA] = 0
  // if n >= 64: rA <- 64 sign bits of rS, XER[CA] = sign bit of rS
  Value* rt = f.LoadGPR(i.X.RT);
  Value* sh =
      f.And(f.Truncate(f.LoadGPR(i.X.RB), INT8_TYPE), f.LoadConstantInt8(0x7F));
  Value* clamp_sh = f.Min(sh, f.LoadConstantInt8(0x3F));
  Value* v = f.Sha(rt, clamp_sh);

  // CA is set if any bits are shifted out of the right and if the result
  // is negative.
  Value* ca =
      f.And(f.IsTrue(f.Shr(rt, 63)), f.CompareNE(f.Shl(v, clamp_sh), rt));
  f.StoreCA(ca);

  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 64-bit arithmetic (sign-propagating) right shift. RA ← (i64)RS >> (RB & 0x7F) with bits shifted in matching the sign bit of RS. Counts ≥ 64 saturate: RA becomes all-ones if RS < 0, else zero.
• XER[CA] is the "lost-ones" indicator. CA = 1 iff RS is negative AND any of the bits shifted out were 1. This makes srad / sradi the standard idiom for "divide negative integer by power of 2 with round-toward-zero" — followed by addze to compensate when CA = 1.
• One expression in Canary, no branches. Canary clamps the count to 63 (sh = RB & 0x7F, Min(sh, 0x3F)) and shifts arithmetically, which saturates counts ≥ 64 to 0 or −1. CA = RS < 0 AND (result << clamp) != RS, i.e. set only for a negative source that shifted out a 1 bit; a count of 0 therefore gives CA = 0.
• Shift count is 7 bits. Same as sldx: RB[57:63].
• Rc=1 CR0 update is 32-bit in Canary (f.UpdateCR(0, v)); it can differ from spec when the high word decides the sign.
• No OE bit.
• Used by signed-divide-by-power-of-2 idiom: srad rA, rS, n; addze rA, rA produces rS / 2^n with truncation toward zero rather than toward -∞.

Related Instructions

• sradix — immediate-shift form (SH 6-bit immediate).
• srawx, srawix — 32-bit arithmetic right shifts.
• srdx — 64-bit logical right shift (no XER[CA]).
• addzex — companion for the divide-rounding idiom.
• sldx — left shift.

IBM Reference

• AIX 7.3 — srad (Shift Right Algebraic Doubleword)