f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
119 lines
4.2 KiB
Markdown
119 lines
4.2 KiB
Markdown
# `xori` — XOR Immediate
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> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x68000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `xori` | `xori` | — | XOR Immediate |
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## Syntax
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```asm
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xori [RA], [RS], [UIMM]
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```
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## Encoding
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### `xori` — form `D`
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- **Opcode word:** `0x68000000`
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- **Primary opcode (bits 0–5):** `26`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | xori: read | Source GPR (alias for RD in some stores). |
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| `UIMM` | xori: read | 16-bit unsigned immediate. Zero-extended. |
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| `RA` | xori: write | Source GPR (`r0`–`r31`). |
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## Register Effects
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### `xori`
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- **Reads (always):** `RS`, `UIMM`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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RA <- (RS) ^ (0x0000 || UIMM)
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`xori`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="xori"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:839`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_alu.cc#L839)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:497`](../../../crates/sylpheed-ppc/src/opcode.rs#L497)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:464`](../../../crates/sylpheed-ppc/src/decoder.rs#L464)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_xori(PPCHIRBuilder& f, const InstrData& i) {
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// RA <- (RS) XOR (i48.0 || UI)
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Value* ra = f.Xor(f.LoadGPR(i.D.RT), f.LoadConstantUint64(XEEXTZ16(i.D.DS)));
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f.StoreGPR(i.D.RA, ra);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **No record form.** Like [`ori`](ori.md), there is no `xori.`. To get a CR0 update follow with `cmpwi` or use [`xorx`](xorx.md) with `Rc=1`.
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- **Immediate is zero-extended** to 64 bits. Only the low 16 bits of `RA` can be flipped; the high 48 bits are passed through from `RS` unchanged.
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- **`xori 0, 0, 0` is a valid NOP encoding** but the canonical NOP is `ori 0, 0, 0`. Disassemblers should still display this as `xori r0, r0, 0` or recognise it as a no-op.
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- **64-bit operation in Canary.** `f.Xor(RS, EXTZ16(UI))` on the full `u64`.
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- **No `XER`, no `CR`** side effects.
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- **`RA = 0` reads `r0`** (not literal zero); see [`ori`](ori.md).
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- **Useful for masked toggle.** `xori rA, rS, mask` flips the bits of `rS` indicated by `mask` (low 16 bits only).
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## Related Instructions
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- [`xoris`](xoris.md) — companion (immediate shifted left 16).
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- [`xorx`](xorx.md) — register-register XOR.
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- [`eqvx`](eqvx.md) — `~(RS ^ RB)`.
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- [`ori`](ori.md), [`andix`](andix.md) — sister immediate logicals.
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## IBM Reference
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- [AIX 7.3 — `xori` (XOR Immediate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-xori-immediate-instruction)
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