Sylpheed/tools/ppc-manual/control/mffsx.md

mffsx — Move from FPSCR

Category: Control / CR / SPR · Form: X · Opcode: 0xfc00048e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mffs	mffsx	—	Move from FPSCR
mffs.	mffsx	Rc=1	Move from FPSCR

Syntax

mffs[Rc] [RD]

Encoding

mffsx — form X

• Opcode word: 0xfc00048e
• Primary opcode (bits 0–5): 63
• Extended opcode: 583
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FPSCR	mffsx: read	Floating-Point Status and Control Register.
FD	mffsx: write	Destination floating-point register.
CR	mffsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mffsx

• Reads (always): FPSCR
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• mffsx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mffsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="mffsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:397
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:172
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1025

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mffsx(PPCHIRBuilder& f, const InstrData& i) {
  Value* v = f.Cast(f.ZeroExtend(f.LoadFPSCR(), INT64_TYPE), FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  if (i.X.Rc) {
    f.CopyFPSCRToCR1();
  }
  return 0;
}

Special Cases & Edge Conditions

• Operation. Reads the 32-bit FPSCR and places it in the low 32 bits of FRT. The high 32 bits of the destination FPR are architecturally undefined; Canary zero-extends the FPSCR to 64 bits and reinterprets that as the FPR's bit pattern, so the high bits are zero. PowerISA explicitly permits implementations to leave anything there.
• Destination is an FPR, not a GPR. Use stfd to spill the FPR to memory and reload via a GPR if the value is needed in the integer file.
• mffs. (Rc=1) updates CR1. The Rc bit copies the high four FPSCR bits (FX, FEX, VX, OX) into CR1's LT/GT/EQ/SO. Canary implements this via CopyFPSCRToCR1.
• No FPSCR side effect. Pure read; FPSCR is not modified (unlike mcrfs, which clears sticky exception bits).
• Canary simplification. Canary keeps FPSCR as a 32-bit field but does not maintain the IEEE-754 sticky bits — its UpdateFPSCR is a stub that only clears FEX/VX. So mffs returns what mtfsf/mtfsfi/mcrfs last wrote (initially 0), zero-extended into the FPR's bit pattern. Real titles use it mostly to save/restore the rounding-mode field around library calls, which works: restoring through mtfsf also reloads the host rounding mode.
• Not synchronising. Reorderable with non-FPU instructions.

Related Instructions

• mtfsfx — write fields of FPSCR from an FPR (the inverse).
• mtfsb0x, mtfsb1x — set/clear individual FPSCR bits.
• mtfsfix — load a 4-bit immediate into one FPSCR field.
• mcrfs — copy an FPSCR field into a CR field (and clear sticky bits).
• mfspr — for non-FPSCR special registers.

mffs is the simplified mnemonic for the base form (Rc=0); mffs. is the recording variant.

IBM Reference

• AIX 7.3 — mffs (Move from FPSCR)
• PowerISA v2.07B, Book I §4.6 — FPSCR layout and the high-half-undefined rule.