Sylpheed/tools/ppc-manual/control/mtfsb1x.md

mtfsb1x — Move to FPSCR Bit 1

Category: Control / CR / SPR · Form: X · Opcode: 0xfc00004c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtfsb1	mtfsb1x	—	Move to FPSCR Bit 1
mtfsb1.	mtfsb1x	Rc=1	Move to FPSCR Bit 1

Syntax

mtfsb1[Rc] [FPSCRD]

Encoding

mtfsb1x — form X

• Opcode word: 0xfc00004c
• Primary opcode (bits 0–5): 63
• Extended opcode: 38
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FPSCRD	mtfsb1x: write	FPSCR destination field.
CR	mtfsb1x: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mtfsb1x

• Reads (always): none
• Reads (conditional): none
• Writes (always): FPSCRD
• Writes (conditional): CR

Status-Register Effects

• mtfsb1x: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtfsb1x

• Canary XML: tools/ppc-instructions.xml — search for mnem="mtfsb1x"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:411
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:180
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1017

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mtfsb1x(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Operation. Sets (writes 1 to) a single named bit of FPSCR. FPSCRD is a 5-bit absolute index (0..31), big-endian (0 = MSB = FX).
• Mnemonic name. "1" denotes the value written, not bit position. Pair with mtfsb0x for clears.
• Restricted bits. PowerISA forbids mtfsb1 from setting FEX (bit 1) or VX (bit 2) directly — both are summary bits derived from other state. mtfsb1 can set FX (bit 0), which is itself a sticky summary; this is occasionally used to force a Program interrupt for testing. ⚠️ Canary does not implement mtfsb1: its emitter is XEINSTRNOTIMPLEMENTED, so translating one logs "Unimplemented instr" and, with the default break_on_unimplemented_instructions, breaks.
• Rc=1. mtfsb1. (Rc=1) updates CR1 with the high four FPSCR bits (FX, FEX, VX, OX) after the set.
• Common use. Force-set a sticky exception bit to test exception-handling code paths. Also seen in floating-point library setup that wants a known FPSCR seed.
• Canary status. Canary does not implement mtfsb1 (XEINSTRNOTIMPLEMENTED), so the bit is never set and will not read back via mffsx.
• Not synchronising. Reorderable.

Related Instructions

• mtfsb0x — clear a single FPSCR bit.
• mtfsfx — write 4-bit FPSCR fields from an FPR.
• mtfsfix — write 4-bit immediate into a single FPSCR field.
• mffsx — read FPSCR.
• mcrfs — FPSCR field → CR field (clears sticky bits).

mtfsb1 is the simplified form (Rc=0); mtfsb1. is the recording variant.

IBM Reference

• AIX 7.3 — mtfsb1 (Move to FPSCR Bit 1)
• PowerISA v2.07B, Book I §4.6 — FPSCR bit definitions and FX/FEX/VX restriction.