Sylpheed/tools/ppc-manual/control/mtfsfx.md

mtfsfx — Move to FPSCR Fields

Category: Control / CR / SPR · Form: XFL · Opcode: 0xfc00058e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtfsf	mtfsfx	—	Move to FPSCR Fields
mtfsf.	mtfsfx	Rc=1	Move to FPSCR Fields

Syntax

mtfsf[Rc] [FM], [FB]

Encoding

mtfsfx — form XFL

• Opcode word: 0xfc00058e
• Primary opcode (bits 0–5): 63
• Extended opcode: 711
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (63)
6	L	field-select behaviour
7–14	FM	FPSCR field mask
15	W	immediate-value flag
16–20	FRB	source FPR
21–30	XO	extended opcode
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FM	mtfsfx: read	8-bit FPSCR field-mask used by mtfsf.
FB	mtfsfx: read	Source B floating-point register.
FPSCR	mtfsfx: write	Floating-Point Status and Control Register.
CR	mtfsfx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mtfsfx

• Reads (always): FM, FB
• Reads (conditional): none
• Writes (always): FPSCR
• Writes (conditional): CR

Status-Register Effects

• mtfsfx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtfsfx

• Canary XML: tools/ppc-instructions.xml — search for mnem="mtfsfx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:416
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:182
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1026

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mtfsfx(PPCHIRBuilder& f, const InstrData& i) {
  if (i.XFL.L) {
    // Move/shift.
    f.StoreFPSCR(
        f.Truncate(f.Cast(f.LoadFPR(i.XFL.RB), INT64_TYPE), INT32_TYPE));
    return 1;
  } else {
    assert_zero(i.XFL.W);
    // Store under control of mask.
    // Expand the mask from 8 bits -> 32 bits.
    uint32_t mask = 0;
    for (int j = 0; j < 8; j++) {
      if (i.XFL.FM & (1 << (j ^ 7))) {
        mask |= 0xF << (4 * j);
      }
    }

    Value* v = f.Truncate(f.Cast(f.LoadFPR(i.XFL.RB), INT64_TYPE), INT32_TYPE);
    if (mask != 0xFFFFFFFF) {
      Value* fpscr = f.LoadFPSCR();
      v = f.And(v, f.LoadConstantInt32(mask));
      v = f.Or(v, f.And(fpscr, f.LoadConstantInt32(~mask)));
    }
    f.StoreFPSCR(v);

    // Update the system rounding mode.
    if (mask & 0x7) {
      f.SetRoundingMode(f.And(v, f.LoadConstantInt32(7)));
    }
  }
  if (i.XFL.Rc) {
    f.CopyFPSCRToCR1();
  }
  return 0;
}

Special Cases & Edge Conditions

• FM is an 8-bit field-mask. Each of the eight bits selects one 4-bit FPSCR field (0..7). FM[0] (0x80) selects FPSCR field 0 (bits 0..3 = FX, FEX, VX, OX), …, FM[7] (0x01) selects FPSCR field 7 (rounding-mode bits RN). Set bits cause that field of FRB's low 32 bits to overwrite the corresponding FPSCR field; clear bits leave the field unchanged.
• Source is the LOW 32 bits of FRB. The high 32 bits are ignored. Software that wants to write a 32-bit pattern typically constructs it in a GPR, stores to memory, and reloads as a double via lfd.
• Most common use: setting rounding mode. Compilers wrap calls to <fenv.h>-style functions with mtfsf 1, fX to update only the rounding-mode field (RN, FPSCR field 7).
• Rc=1 updates CR1. mtfsf. copies FPSCR's top 4 bits (FX, FEX, VX, OX) into CR1 after the write.
• L/W bits. PowerISA v2.05+ adds L=1 to mean "write all FPSCR bits regardless of FM" and W=1 to select the upper or lower 32 bits. Canary handles L=0; its L=1 path writes FPSCR but still reports the instruction as unimplemented, and W is only asserted to be zero.
• Canary behaviour. Canary applies the field mask correctly and, when the mask covers RN, reloads the host rounding mode, so conversions and arithmetic that round follow the new mode. The exception bits are another matter: Canary's UpdateFPSCR is a stub, so they are never set by FP arithmetic.
• Not synchronising. Reorderable; PowerISA recommends an isync after FPSCR changes that affect subsequent FP behaviour.

Related Instructions

• mtfsfix — write a 4-bit immediate into one FPSCR field (no FPR source needed).
• mtfsb0x, mtfsb1x — single-bit FPSCR write.
• mffsx — read FPSCR into an FPR.
• mcrfs — copy FPSCR field → CR field.

mtfsf is the simplified form (Rc=0); mtfsf. is the recording variant.

IBM Reference

• AIX 7.3 — mtfsf (Move to FPSCR Fields)
• PowerISA v2.07B, Book I §4.6.6 — mtfsf definition and L/W extensions.