Sylpheed/tools/ppc-manual/fpu/fctiwx.md

fctiwx — Floating Convert to Integer Word

Category: Floating-Point · Form: X · Opcode: 0xfc00001c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fctiw	fctiwx	—	Floating Convert to Integer Word
fctiw.	fctiwx	Rc=1	Floating Convert to Integer Word

Syntax

fctiw[Rc] [FD], [FB]

Encoding

fctiwx — form X

• Opcode word: 0xfc00001c
• Primary opcode (bits 0–5): 63
• Extended opcode: 14
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fctiwx: read	Source B floating-point register.
FD	fctiwx: write	Destination floating-point register.
CR	fctiwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fctiwx: write	Floating-Point Status and Control Register.

Register Effects

fctiwx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fctiwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fctiwx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fctiwx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:308
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:72
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1014

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fctiwx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- double_to_signed_int32( frB )
  return InstrEmit_fctiwxx_(f, i, ROUND_DYNAMIC);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_fpu.cc:289) ──
int InstrEmit_fctiwxx_(PPCHIRBuilder& f, const InstrData& i,
                       RoundMode round_mode) {
  auto end = f.NewLabel();
  auto isnan = f.NewLabel();
  Value* v;
  f.BranchTrue(f.IsNan(f.LoadFPR(i.X.RB)), isnan);
  v = f.Convert(f.LoadFPR(i.X.RB), INT32_TYPE, round_mode);
  v = f.Cast(f.SignExtend(v, INT64_TYPE), FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  f.Branch(end);
  f.MarkLabel(isnan);
  v = f.Cast(f.LoadConstantUint32(0x80000000u), FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  f.MarkLabel(end);
  return 0;
}

Special Cases & Edge Conditions

• binary64 → 32-bit signed integer, current rounding mode. Result is rounded per FPSCR[RN] and packed into the low 32 bits of the destination FPR. The high 32 bits are architecturally undefined per PowerISA; Canary sign-extends the 32-bit result into them (for a NaN input it stores 0x0000_0000_8000_0000).
• Saturation in Canary. Its x64 backend clamps the input to (double)0x7FFFFFFF (vminsd) before cvtsd2si, which already returns 0x80000000 for large negatives — so both directions saturate as PowerPC specifies.
• NaN sentinel. Canary branches on NaN explicitly and stores 0x0000_0000_8000_0000 — i32::MIN in the low word, PPC's VXCVI sentinel, with a zero high word. For ordinary results it instead sign-extends the 32-bit integer into the high word (SignExtend(v, INT64)); PowerPC leaves those bits undefined.
• Rounding follows FPSCR[RN] in Canary. ROUND_DYNAMIC converts under the host rounding mode Canary sets from mtfsf/mtfsfi, so default round-to-nearest gives 0/2/2 for 0.5/1.5/2.5, as on PPC.
• FPSCR[RN] honoured in Canary. ROUND_DYNAMIC converts under the host rounding mode, which Canary loads from FPSCR[RN] whenever the guest writes it through mtfsf/mtfsfi.
• FPSCR side effects. PPC sets XX/FX on inexact and VXCVI on NaN/out-of-range; Canary raises no FPSCR bits (UpdateFPSCR is a stub).
• Rc=1 (fctiw.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 14. Reads FRB only.
• Common pairing. Followed by stfiwx to store the low-32-bit integer to memory (stfd would write the doubleword including the high bits, which on hardware are undefined).

Related Instructions

• fctiwzx — 32-bit integer with round-toward-zero (truncation).
• fctidx, fctidzx — 64-bit integer variants.
• fcfidx — inverse direction (i64 → f64); for i32 → f64, sign-extend then fcfid.
• stfiwx — store low-32-bits FPR (the canonical companion to fctiw/fctiwz).
• mffsx, mtfsfx — control FPSCR[RN], which Canary honours for this instruction.

IBM Reference

• AIX 7.3 — fctiw (Floating Convert to Integer Word)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (high 32 bits are architecturally undefined; only stfiwx is the spec-blessed consumer).