Sylpheed/tools/ppc-manual/fpu/fnmaddx.md

fnmaddx — Floating Negative Multiply-Add

Category: Floating-Point · Form: A · Opcode: 0xfc00003e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fnmadd	fnmaddx	—	Floating Negative Multiply-Add
fnmadd.	fnmaddx	Rc=1	Floating Negative Multiply-Add

Syntax

fnmadd[Rc] [FD], [FA], [FC], [FB]

Encoding

fnmaddx — form A

• Opcode word: 0xfc00003e
• Primary opcode (bits 0–5): 63
• Extended opcode: 31
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fnmaddx: read	Source A floating-point register (fr0–fr31).
FC	fnmaddx: read	Source C floating-point register (for madd-style ops).
FB	fnmaddx: read	Source B floating-point register.
FD	fnmaddx: write	Destination floating-point register.
CR	fnmaddx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fnmaddx: write	Floating-Point Status and Control Register.

Register Effects

fnmaddx

• Reads (always): FA, FC, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fnmaddx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- −((FRA × FRC) + FRB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fnmaddx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fnmaddx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:213
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:86
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1045

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fnmaddx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- -([frA x frC] + frB)
  Value* v = f.Neg(
      f.MulAdd(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRC), f.LoadFPR(i.A.FRB)));
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}

Special Cases & Edge Conditions

• Single rounding step, then sign flip. Computes −((FRA × FRC) + FRB) with one fused rounding for the FMA; the final negation is a bit-pattern sign-flip and does not introduce additional rounding error. Canary emits Neg(MulAdd(a, c, b)), fused only on FMA3 hosts (vfmadd213sd, otherwise vmulsd + vaddsd).
• Sign of NaN. Per PowerISA, fnmadd does not flip the sign of a NaN result. Canary's Neg (vxorpd with the sign mask) does; this is observable through bit-level inspection but not through arithmetic comparisons. Canary quirk — title code that inspects NaN sign bits will diverge.
• Operand order. Assembler: FD, FA, FC, FB.
• Invalid operations. Same as fmadd: VXIMZ for 0×∞, VXISI for opposing-infinity collision. Quiet NaN result.
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX, OX, UX, XX, VXIMZ, VXISI, VXSNAN. Canary does not (UpdateFPSCR is a stub).
• Rc=1 (fnmadd.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• NaN propagation. Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
• Use case. Computing -a*c - b directly without an intermediate negate. Useful in iterative solvers and in transforming polynomial coefficients.
• Denormal flush. That Xenon boots with FPSCR[NI]=1 is unverified. Canary starts every guest thread in IEEE mode (MXCSR 0x1F80; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (MXCSR.FZ) only when the guest sets NI through mtfsf/mtfsfi.

Related Instructions

• fnmaddsx — single-precision sibling.
• fmaddx, fmsubx, fnmsubx — other fused multiply-add variants:
  • fmadd = (A×C) + B
  • fmsub = (A×C) − B
  • fnmsub = −((A×C) − B)
• fnegx, fnabsx — sign-bit operations on FPRs.
• fmulx, faddx — non-fused decomposition.

IBM Reference

• AIX 7.3 — fnmadd (Floating Negative Multiply-Add)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (note: PowerISA specifies the negation does not flip NaN sign bits).